Pulse code sequence analyzer

• US 6,115,416 A
• Filed: 11/13/1998
• Issued: 09/05/2000
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Richard N. Nottenburg, Vladimir Katzman
• Inventors: Katsman, Vladimir, Nottenburg, Richard N.
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): PHU, PHUONG M
• Application Number:
  US09/191,783
• Time in Patent Office: 662 Days
• Field of Search: 375/224, 714/704
• US Class Current: 375/224
• CPC Class Codes: H04L 1/20 using signal quality detector

Abstract

A pulse code analyzer for analyzing data transmitted by transmitter/receivers on a transmission facility interconnecting the transmitter/receivers. The analyzer apparatus has a data converter with a reference and an auxiliary channel for receiving the data and clock apparatus for recovering a clock signal from the data and generating variable time delayed subtone clock signals to the data converter reference and auxiliary channels. Processor apparatus coupled to the data converter and clock means controls a time delay between the subtone clock signals and the voltage level of data received by the channels to detect errors occurring in the received data and records the detected errors in counter apparatus coupled to the data converter channels and clock apparatus. The processor apparatus records a three dimensional matrix of the recorded errors determining a probability predicting the data errors.

Claims

1. A pulse code analyzer for analyzing data, comprising:

data converter means for receiving the data,

clock means for recovering a clock signal from the data and applying generated subtone clock signals to the data converter means,

counter means coupled with the data converter means and clock means for recording errors occurring in the data, and processor means coupled to the counter, data converter and clock means for controlling the clock and data converter means to detect errors occurring in the data received by the data converter means and for recording a matrix of the recorded errors determining a probability predicting the data errors, the data converter means including a reference and an auxiliary channel, each for receiving the data

each reference and each auxiliary channel includes a voltage comparator controlled by the processor means for determining a varying voltage level of data received by each of the reference and auxiliary channels.

2. The pulse code analyzer set forth in claim 1 wherein the clock means comprises buffer means for dividing the recovered clock signal into a pair of subtone clock signals.

3. The pulse code analyzer set forth in claim 2 wherein the clock means comprises a fixed delay means connected to the buffer means for inserting a fixed time delay into a first one of the subtone clock signals.

4. The pulse code analyzer set forth in claim 3 wherein the clock means comprises a variable delay means controlled by the processor means and connected to the fixed delay means for inserting a variable time delay following the fixed time delay into the first subtone clock signal and applying the time delayed first clock signal to the data converter means.

5. The pulse code analyzer set forth in claim 4 wherein the clock means further comprises another variable delay means controlled by the processor means and connected to the buffer means for inserting a variable time delay into a second one of the subtone clock signals and applying the time delayed second clock signal to the data converter means.

6. The pulse code analyzer set forth in claim 5 wherein the processor means comprises digital-to-analog means for controlling the variable delay means to insert variable time delays between the first and second subtone clock signals applied to the data converter means.

7. The pulse code analyzer set forth in claim 6 wherein the data converter means comprises reference and auxiliary channel logic means enabled by the first and second subtone clock signals for detecting errors occurring in the data received by the data converter means during a variable length of time between the inserted variable time delays of the first and second subtone clock signals.

8. The pulse code analyzer set forth in claim 7 wherein the counter means comprises logic means connected with the data converter reference and auxiliary channel logic means and enabled by the clock means for enabling the counting means to count the errors detected during the variable length of time.

9. The pulse code analyzer set forth in claim 8 wherein the processor means comprises memory means for recording the counted errors in a three dimensional matrix format of voltage amplitude versus time enabling the processing means to determine the probability predicting the data errors.

10. The pulse code analyzer set forth in claim 2 wherein each reference and auxiliary channel comprises a pair of interconnected bistable devices with a first one of the bistable devices having an input connected to one of the voltage comparators.

11. The pulse code analyzer set forth in claim 10 wherein the data converter means comprises a reference channel first bistable device having another input connected to receive a fixed and variable time delayed first one of the subtone clock signals.

12. The pulse code analyzer set forth in claim 11 wherein the data converter means comprises an auxiliary channel first bistable device having another input connected to receive a variable time delayed second one of the subtone clock signals.

13. The pulse code analyzer set forth in claim 12 wherein the data converter means reference and auxiliary channels each comprises a second bistable device having one input connected to an output of the channel first bistable device corresponding with the device input corresponding with the channel voltage comparator and another input connected with an inverted second subtone clock signal.

14. The pulse code analyzer set forth in claim 13 wherein the clock means comprises a fixed delay line for inserting a fixed time delay into the first substone clock signal, and a pair of variable delay lines each for inserting a variable time delay into the first and second subtone clock signals.

15. The pulse code analyzer set forth in claim 14 wherein the processor means comprises a programmable digital processor for controlling the clock means variable delay lines to insert a variable time length between the subtone clock signals and for controlling the reference and auxiliary channel voltage comparators to vary the voltage level of data received by the channels to detect errors occurring in the received data during the variable time delay and to record a three dimensional matrix of the errors recorded by the counter means determining a probability predicting the data errors in the analyzed data.

16. A pulse code analyzer for analyzing data comprising:

data converter means having a reference and an auxiliary channel for receiving the data,

clock means for recovering a clock signal from the data and generating a pair of subtone clock signals and applying ones of the subtone clock signals to the reference and auxiliary channels,

counter means coupled with the data converter means and clock means for recording errors occurring in the data, and

processor means coupled to the counter, data converter and clock means for controlling the clock and data converter means to insert time delays between the subtone clock signals enabling the data converter means to detect errors occurring in the received data and record the detected errors in the counter means enabling the processor means to record a three dimensional matrix of the counted errors and determine a probability predicting errors occurring in the analyzed data.

17. The pulse code analyzer set forth in claim 16 wherein each reference and auxiliary channel comprises a voltage comparator controlled by the processor means for controlling the voltage amplitude of data received by each channel.

18. The pulse code analyzer set forth in claim 17 wherein the clock means comprises a fixed delay line for inserting a fixed time delay in one of the subtone clock signals.

19. The pulse code analyzer set forth in claim 18 wherein the clock means comprises a pair of variable delay lines controlled by the processor means for inserting variable time delays into each of the subtone clock signals.

20. The pulse code analyzer set forth in claim 19 wherein the processor means comprises digital-to analog means coupled with the variable delay lines and with the voltage comparators for enabling the processor means to control the variable delay lines time delays and the voltage level of data received by the reference and auxiliary channels.

21. The pulse code analyzer set forth in claim 20 wherein the processor means comprises a programmable digital processor, and a data bus coupling the processor with the counter and digital-to-anlog means.

22. The pulse code analyzer set forth in claim 21 wherein the digital processor comprises memory means for storing the counter means detected errors in a three dimensional matrix configuration of voltage level versus time wherein the matrix configuration defines the probability predicting the data errors.

23. A pulse code analyzer for analyzing data, comprising:

data converter means having a reference and an auxiliary channel for receiving the data,

clock means for generating a pair of subtone clock signals separated by a time delay and applying the separated subtone clock signals to the reference and auxiliary channels to enable the data converter means to detect errors appearing in the analyzed data,

counter means coupled with the reference and auxiliary channels and clock means for recording the detected errors, and

processor means coupled to the counter, data converter and clock means for controlling the clock means to vary the time delay between the subtone clock signals and to store errors detected in varying time delays as errors in a matrix of data voltage versus time determining a probability predicting errors in the analyzed data.

24. The pulse code analyzer set forth in claim 23 wherein each of data converter means reference and auxiliary channels comprise a voltage comparator device for controlling an input voltage level of the received data.

25. The pulse code analyzer set forth in claim 24 wherein the clock means comprises circuit means for recovering a clock signal from the received data and dividing the recovered clock signal by a predefined number N to generate the pair of subtone clock signals.

26. The pulse code analyzer set forth in claim 25 wherein the clock means comprise a fixed delay line for inserting a fixed length time delay in one of the subtone clock signals applied to the reference channel.

27. The pulse code analyzer set forth in claim 26 wherein the clock means comprise a pair of variable delay lines each corresponding with one of the reference and auxiliary channels for inserting variable time delays in the subtone clock signals applied to the channels.

28. The pulse code analyzer set forth in claim 27 wherein the processor means comprise a programmed digital processor coupled to the counter, data converter and clock means for controlling the voltage comparators to vary the level of the data voltage applied to the reference and auxiliary channels and for controlling the variable delay lines to vary a time delay between the subtone clock signals.

29. The pulse code analyzer set forth in claim 28 wherein the processor means comprise a digital bus interconnecting the programmed digital processor with the counter, clock and data converter means.

30. The pulse code analyzer set forth in claim 29 wherein the processor means comprise digital-to-analog means coupled to the digital bus and responsive to the programmed processor for generating analog signals in response to digital information received from the programmed processor for controlling the variable delay lines and the voltage comparators.

31. The pulse code analyzer set forth in claim 30 wherein the counter means comprise a ripple counter connected to the digital bus, and

logic means connecting the ripple counter to the reference and auxiliary channels and enabled by an inversion of the subtone clock signal applied to the auxiliary channel for recording the detected errors in the ripple counter.

32. The pulse code analyzer set forth in claim 30 further comprising digital-to-analog means coupled to the digital processor and responsive to digital information received from the processor for generating analog signals controlling the variable delay lines and the voltage comparators to detect errors in the received data.

33. A pulse code analyzer for analyzing optical and voltage data, comprising:

data converter means having a reference and an auxiliary channel for receiving the data with each channel having a voltage comparator device for controlling an input voltage level of the data received by the channels,

clock means for recovering a clock signal from the received data and dividing the recovered clock signal by a predefined number N to generate a pair of subtone clock signals and wherein the clock means has a fixed delay line for inserting a fixed length time delay in one of the subtone clock signals and a pair of variable delay lines each corresponding with one of the reference and auxiliary channels for inserting variable time delays in the subtone clock signals and applying each of the time delayed subtone clock signals to one of the reference and auxilary channels,

counter means having a ripple counter connected to logic means coupled with the reference and auxiliary channels and enabled the subtone clock signal applied to the auxiliary channel and inverted as an input to the logic means for recording data errors detected by the data converter means in the ripple counter during a time delay between the pair of subtone clock signals, and

a programmed digital processor coupled to the ripple counter, voltage comparators and variable delay lines for controlling the voltage comparators to vary the level of the data voltage applied to the reference and auxiliary channels and for controlling the variable delay lines to vary the time delay between the subtone clock signals enabling the ripple counter to record data errors and to store the recorded errors in a memory of the processor as a dimensional matrix of errors defining a probability predicting the data errors.

34. A method of analyzing data comprising the steps of

receiving the data in a voltage comparator of a reference and auxiliary channel,

recovering a clock signal from the received data,

dividing the recovered clock signal by a predefined number N and generating a pair of subtone clock signals therefrom,

inserting a fixed length time delay and a variable time delay in a subtone signal applied to the reference channel and another variable time delay in the other subtone clock signal applied to the auxiliary channel wherein the subtone clock signals are separated by a variable time delay,

varying the voltage level of the channel voltage regulators and the length of the variable time delays in time thereby changing the time length of the channel separating variable time delay,

detecting and counting errors appearing in the received data during the variable time delay, and

recording the counted errors in a memory of a processor as a three dimensional matrix of the counted errors in voltage amplitude versus time thereby enabling the processor to determine a probability predicting the data errors.

35. The method of analyzing data set forth in claim 34 wherein said varying step comprises the step of generating analog signals in response to digital signals received from the processor for controlling the voltage level of the channel voltage comparators and the time delay of the variable time delays in real time.