Semiconductor tester with remote debugging for handler

• US 6,115,645 A
• Filed: 08/18/1997
• Issued: 09/05/2000
• Est. Priority Date: 08/18/1997
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Berar, Andrei
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): Bahta, Kidest
• Application Number:
  US08/914,581
• Time in Patent Office: 1,114 Days
• Field of Search: 700/121, 700/95, 700/96, 700/108, 700/109, 700/107, 700/118, 700/119, 414/937-940, 318/570
• US Class Current: 700/121
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits

Abstract

A semiconductor tester at a first station includes a device handler operating under control of a first computer located at the first station. The handler is provided with a video camera having an output connected to a port of the first computer. A second computer, which includes a display monitor, is located at a second station, which is remote from the first station, and the first and second computers are connected in a computer network. The video camera is employed to acquire an image of the handler and the video camera provides the first computer with video data representative of this image. The video data is transmitted over the computer network to the second computer and is provided to the display monitor, whereby the image acquired by the video camera can be viewed on the display monitor. Information regarding operation of the device handler is transmitted from the second station to the first station.

Claims

1. A method of monitoring a semiconductor integrated circuit tester operating at a first station under control of a first computer located at the first station, the method comprising:

providing a video camera located at the first station, the video camera having an output connected to a port of the first computer,

providing a second computer located at a second station, which is remote from the first station, wherein the first and second computers are connected in a computer network and the second computer includes a display monitor,

employing the video camera to acquire an image of the tester, whereby the video camera provides the first computer with video data representative of said image,

transmitting said video data over the computer network to the second computer,

providing said video data to the display monitor,

employing the display monitor to display the image represented by said video data, whereby the image acquired by the video camera can be viewed on the display monitor, and

transmitting information from the second station to the first station regarding operation of the semiconductor tester.

2. A semiconductor integrated circuit test facility, for testing integrated circuit devices, comprising:

a device handler for receiving integrated circuit devices at an input station, delivering the devices to a test location, removing the devices from the test location and transporting the devices to an output station for further processing, and

a video camera selectively positionable to acquire an image of the handler,

and wherein operation of the handler is controlled by a computer having a handler CPU, the handler CPU is connected over a computer network to a supervisory computer at a remote location, the supervisory computer includes a display monitor, the video camera is connected to the handler CPU and supplies the acquired image over the computer network to the supervisory computer, and the display monitor displays the acquired image for viewing at the remote location.

3. A semiconductor test facility according to claim 2, wherein the device handler is located in a clean room and the supervisory computer is located outside the clean room.

4. A semiconductor test facility according to claim 2, wherein the supervisory computer includes a CPU and the facility further comprises a second video camera having an output connected to the CPU of the supervisory computer and the handler computer includes a display monitor.

5. A semiconductor test facility according to claim 2, comprising a microphone integrated with the video camera for acquiring an acoustic signal generated in the vicinity of the handler and wherein the supervisory computer includes a transducer means for receiving audio data from the handler CPU and reproducing the acoustic signal at the remote location.

6. A semiconductor test facility according to claim 5, wherein the supervisory computer includes a CPU and the facility further comprises a second video camera having an output connected to the CPU of the supervisory computer, a second microphone is integrated with the second video camera for acquiring an acoustic signal generated in the vicinity of the supervisory computer, and the handler computer includes a transducer means for receiving audio data from the supervisory computer over the network and reproducing the acoustic signal in the vicinity of the handler.

7. A semiconductor integrated circuit test facility comprising:

a plurality of semiconductor integrated circuit testers in a clean room, each tester including an integrated circuit device handler which is controlled by a dedicated computer having a handler CPU and a video camera connected to the handler CPU and positionable to capture an image of a selected region of the handler,

a supervisory computer located outside the clean room and having a supervisory CPU and a display monitor, and

a network connecting each of the handler CPUs to the supervisory CPU, whereby the display monitor of the supervisory computer displays an image of a selected handler, as captured by the video camera of the tester that includes the selected handler.