LOADRS instruction and asynchronous context switch
First Claim
1. In a processor to execute a programmed flow of instructions, said processor including a register stack (RS) and a register stack engine (RSE) to exchange information between said RS and a storage area, a method for returning from an interrupting context to an interrupted context, the method comprising:
- generating a first pointer that points to a location in the storage area where dirty registers of an interrupted context are stored;
determining whether a mathematical relation is valid between said first pointer PTR and a second pointer pointing to a location in said storage area from where the RSE configured to load a programmable number of dirty register values into the RS;
if said mathematical relation is valid, causing said second pointer to point to a next location in said storage area; and
loading a register of said RS with a content of said next location in said storage area.
1 Assignment
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Accused Products
Abstract
A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a register stack (RS) and a register stack engine (RSE) to exchange information between the RS and the storage area. The method includes the following steps: (a.) A first pointer (PTR) is generated. The pointer (PTR) points to a location in the storage area where dirty registers (previously unsaved) of an interrupted context are stored; (b.) It is determined whether a mathematical relation is valid between the first pointer and the second pointer (BSPLOAD) to a location in the storage area from where the RSE is configured to load dirty register values into the RS; (c) The second pointer is caused to point to a next location in the storage area if the relation is valid; and (d) A register of the RS is loaded with a content of the next location in the storage area until the mathematical relation becomes invalid.
34 Citations
12 Claims
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1. In a processor to execute a programmed flow of instructions, said processor including a register stack (RS) and a register stack engine (RSE) to exchange information between said RS and a storage area, a method for returning from an interrupting context to an interrupted context, the method comprising:
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generating a first pointer that points to a location in the storage area where dirty registers of an interrupted context are stored; determining whether a mathematical relation is valid between said first pointer PTR and a second pointer pointing to a location in said storage area from where the RSE configured to load a programmable number of dirty register values into the RS; if said mathematical relation is valid, causing said second pointer to point to a next location in said storage area; and loading a register of said RS with a content of said next location in said storage area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A processor to execute a programmed flow of instructions, said processor comprising:
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a register stack (RS) having a portion to store dirty registers; a register stack engine (RSE) to exchange information between a storage area and said RS in one of instruction execution dependent and independent modes; and a load control circuit to generate a first pointer to a location in the storage area where dirty registers of an interrupted context are stored, to determine whether a mathematical relationship is valid between said first pointer and a second pointer to an address from where the RSE configured to load values to the RS and, while said mathematical relation is valid, to cause said first pointer to point to a next location in said storage area and to load a register of said RS with a content of the storage area to which said first pointer points until said mathematical relation is invalid. - View Dependent Claims (11)
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12. In a processor to execute a programmed flow of instructions, said processor including a register stack (RS) to store therein information related to interrupting and interrupted contexts, and a register stack engine (RSE) to exchange said information, between said RS and a backing store (BS) of said interrupting context, a method for returning to said interrupting context comprising:
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determining whether a specified number of registers of said interrupted context is stored in said RS; if said specified number of registers is not stored in the RS, loading, from said BS a number of registers, of said specified number of registers, that are missing from said RS; and invalidating registers of said RS that are stored beyond a predetermined address.
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Specification