Memory paging scheme for 8051 class microcontrollers

• US 6,115,814 A
• Filed: 11/14/1997
• Issued: 09/05/2000
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Lieber, Timothy, Morris, Timothy J.
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): OMAR, OMAR B
• Application Number:
  US08/971,056
• Time in Patent Office: 1,026 Days
• Field of Search: 713/1, 713/2, 713/100, 710/49, 710/130, 710/261, 710/262
• US Class Current: 713/2
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 9/24 Loading of the microprogram

Abstract

A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Claims

1. A computer system comprising:

a microcontroller;

a write-protected memory coupled to said microcontroller, said write-protected memory having executable boot code for the computer system;

a rewriteable memory coupled to said microcontroller, said rewriteable memory receiving and storing application code for the computer system;

a jump function in said write-protected memory and in said rewriteable memory, said jump function for movement between said write protected memory and said rewritable memory; and

,

a switch coupled to said microcontroller, said switch operable in response to said jump function to switch operation of said microcontroller between said write-protected memory and said rewriteable memory,

wherein said computer system has good boot code in said write-protected memory, and said boot code is executable while the application code is unavailable in said rewriteable memory.

2. The computer system of claim 1 wherein said microcontroller comprises a "Harvard" architecture chip.

3. The computer system of claim 2 wherein said chip is an 8051 chip.

4. The computer system of claim 2 wherein said chip is an 8052 chip.

5. The computer system of claim 2 wherein said chip is an 8031 chip.

6. The computer system of claim 1 wherein said write-protected memory is an EPROM.

7. The computer system of claim 1 wherein said rewriteable memory is an EEPROM.

8. The computer system of claim 1 wherein the said jump function further comprises a NOP command and a jump to reset command.

9. In a system having a write-protected memory, a reprogrammable memory and an SRAM coupled to a microcontroller, the write-protected memory containing a system boot code, a method for reprogramming the reprogrammable memory, comprising the steps of:

executing the boot code from the write-protected memory;

checking the reprogrammable memory for a valid application program;

if the application program is not valid, waiting for new application code; and

,

if the application program is valid, switching from the write-protected memory to the reprogrammable memory by executing a jump function from the write-protected memory.