Integrated circuit for coupling a microcontrolled control apparatus to a two-wire bus

• US 6,115,831 A
• Filed: 03/26/1997
• Issued: 09/05/2000
• Est. Priority Date: 03/26/1996
• Status: Expired due to Term

• Current Assignee: Daimler AG (Mercedes-Benz Group AG)
• Original Assignee: DaimlerChrysler AG (Mercedes-Benz Group AG)
• Inventors: Hanf, Peter, Minuth, Jurgen, Setzer, Jurgen
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Baderman, Scott T.
• Application Number:
  US08/825,028
• Time in Patent Office: 1,259 Days
• Field of Search: 395/183.19, 395/185.09, 395/182.01, 395/182.02, 709/230, 709/239, 710/105, 710/128
• US Class Current: 714/43
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25032 CAN, canbus, controller area network bus
• CPC Class Codes: G05B 2219/25182 Serial between host and modules, nodes, parallel in node to microcontroller
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

An integrated semiconductor circuit for an electronic control unit has a microcontroller with a bus protocol function for communicating with other microcontrolled control units via a Controller Area Network (CAN) by way of a two-wire bus. The invention includes a bus-fault-tolerant transceive function which permits communication even when a bus fault is present. A bus fault recognition and response device disconnects the bus from its normal connections and alters its termination characteristics when a fault is detected.

Claims

1. Integrated semiconductor circuit for an electronic control unit having a microcontroller with a bus protocol function and being coupled in communication with other control units, each having a microcontroller with a bus protocol function, by way of a two wire bus to form a Controller Area Network (CAN) in which bus communication takes place serially in a protocol-based manner, by means of alternative communication modes, said semiconductor circuit comprising:

a receiving device having two inputs for connection to wires of the two wire bus and an output for connection to a receiving input of the bus protocol function;

a transmitting device having an input for connection to a transmitting output of the bus protocol function and two outputs for connection to the wires of the two wire bus;

each of said transmitting and receiving devices having a configuration which is variable to implement different communication modes via said two wire bus;

means operative upon occurrence of a bus fault which impairs normal bus communication via both bus wires, for adjusting the receiving device and the transmitting device to implement a best still viable mode for emergency bus communication;

a bus fault recognition device for detecting occurrence of a bus fault;

a bus fault analysis device responsive to information from said bus fault recognition device for preparing and outputting at least one error or interruption signal for supply to the microcontroller;

first and second termination elements; and

a bus termination switching device having a configuration which can be varied in response to information from said bus fault recognition device for selectively connecting said first and second termination elements to respective ones of said two bus wires.

2. Integrated semiconductor circuit according to claim 1 further comprising:

an input for ground;

a first supply input for a higher operating voltage; and

a second supply input for a lower operating voltage.

3. Integrated semiconductor circuit according to claim 1 wherein said bus termination switching device comprises first and second alternate termination elements integrated therein, and at least a switch for connecting at least one of said alternate termination elements to a wire of said two wire bus as a function of a type of recognized bus fault.

4. Integrated semiconductor circuit according to claim 3, wherein the first alternate termination element comprises an impressed current source.

5. Integrated semiconductor circuit according to claim 3 wherein the first alternate termination element comprises a high-ohmic resistor.

6. Integrated semiconductor circuit according to claim 3, wherein the second alternate termination element comprises an impressed current source.

7. Integrated semiconductor circuit according to claim 3, wherein the second alternate termination element comprises a high-ohmic resistor.

8. Integrated semiconductor circuit according to claim 2, wherein the first termination element is connected to the higher operating voltage.

9. Integrated semiconductor circuit according to claim 1, wherein the means for adjusting the receiving device are assigned respectively to the receiving device and the transmitting device, whereby the receiving device is autonomically self-adjusting independently of the transmitting device.

10. Integrated semiconductor circuit according to claim 9, wherein said adjustment takes place within a bus-bit interval.

11. Integrated semiconductor according to claim 9, wherein said adjustment takes place without bus message losses.

12. Integrated semiconductor circuit according to claim 1, further comprising a wakeup recognition device, wherein:

outputs of the bus fault analysis device and the wakeup recognition device are logically linked to generate an error/interruption signal which is supplied to the microcontroller.

13. Integrated semiconductor circuit according to claim 2, wherein when the higher operating voltage drops below a predetermined limit value, the transmitting device is automatically disconnected from the bus.

14. Integrated semiconductor circuit according to claim 2, wherein when the lower operating voltage drops below a predetermined limit value, the transmitting device is automatically disconnected from the bus.

15. Integrated semiconductor circuit according to claim 13, wherein said disconnection takes place by blocking a control input for active connection of the transmitting device to the two wire bus.

16. Integrated semiconductor circuit according to claim 1, further comprising a device which blocks a current supply to the transmitting device as a function of detected faults.

17. Integrated semiconductor circuit according to claim 1, further comprising a device which blocks a current supply to the transmitting device upon recognition of an intrinsic error of the semiconductor circuit.

18. Integrated semiconductor circuit according to claim 16, wherein blocking of the current supply to the transmitting devices causes them to be disconnected from the bus.

19. Integrated semiconductor circuit according to claim 1, further comprising:

a monitoring device for detecting a voltage drop below, or an increase which exceeds, predetermined limit values; and

an analysis device for generating and sending at least one error/interruption signal to the microcontroller in response to information from said monitoring device.

20. Integrated semiconductor circuit according to claim 2, further comprising

a monitoring device for detecting a failure of a voltage supplied to said semiconductor circuit, by monitoring the higher operating voltage to detect drops below a first limit value;

and

an analysis device for the generating and sending at least one error/interruption signal to the microcontroller in response to information from the monitoring device.

21. Integrated semiconductor circuit according to claim 20, wherein

said monitoring device also monitors the lower operating voltage of the microcontroller to detect a drop below a second limit value;

and

said analysis device generates and sends of at least an error/interruption signal to the microcontroller when said operating voltage drops below said limit value.

22. Integrated semiconductor circuit according to claim 21, further comprising a logic device which generates an error/interruption signal in response to a drop of said voltages below both limit values.

23. Integrated semiconductor circuit according to claim 1, further comprising a monitoring device for detecting a failure of a voltage supply for said integrated circuit in response to a drop of a first supply voltage for said semiconductor circuit below a first limit value, wherein:

outputs of the bus error analysis device and the monitoring device are logically linked to control and send an error/interruption signal to the microcontroller.

24. Integrated semiconductor circuit according to claim 23, wherein said monitoring device also detects a drop of a second supply voltage for said semiconductor circuit below a second limit value, wherein the bus error analysis device and the monitoring device generate and send an error/interruption signal to the microcontroller.

25. Integrated semiconductor circuit according to claim 1, further comprising filter elements which are switched so that one of them is operative at least between one bus wire and a corresponding one of two inputs of the receiving device or the bus fault recognition device.

26. Integrated semiconductor circuit according to claim 1, wherein the receiving device and transmitting device are constructed without external protective wiring in a nondestructive manner, error-tolerant with respect to possible errors bus-wide.

27. Integrated semiconductor circuit according to claim 1, which is monolithically integrated.

28. Integrated semiconductor circuit according to claim 27, which is monolithically integrated on a semiconductor substrate together with another semiconductor circuit function.

29. Integrated semiconductor circuit according to claim 27, which is integrated on a semiconductor chip, and is designed as a compilable standard cell.

30. Integrated semiconductor circuit for an electronic control unit having a microcontroller with a bus protocol function and being coupled in communication with other control units, each having a microcontroller with a bus protocol function, by way of a two wire bus to form a Controller Area Network (CAN) in which bus communication takes place serially in a protocol-based manner by means of alternative communication modes, wherein:

said semiconductor circuit has at least two different operating modes, a transmitting and receiving NORMAL mode and a dormant SLEEP mode, and comprises

a receiving device having two inputs connected to wires of the two wire bus and an output for the connection to a reception input of the bus protocol function;

a transmitting device having an input for connection to a transmitting output of the bus protocol function and two outputs connected to the wires of the two wire bus;

an input for reception of at least one selection signal from the microcontroller for selection of one of said operating modes;

an input for the reception of locally generated local wakeup signal;

a wakeup recognition device connected with the two wire bus and with the input for reception of a wakeup signal;

a switching device for providing a switching signal; and

a wakeup analysis device for generating and sending to the microcontroller an error/interruption signal when said semiconductor circuit is in the "SLEEP" operating mode and a wakeup signal is recognized by the wakeup recognition device from said bus or from said input for reception of a local wakeup signal.

31. Integrated semiconductor circuit according to claim 30 further comprising:

an input for ground;

a first supply input for a higher operating voltage; and

a second supply input for a lower operating voltage.

32. Integrated semiconductor circuit according to claim 31 wherein:

in the "SLEEP" operating mode, the supply input for the lower operating voltage is not energized.

33. Integrated semiconductor circuit according to claim 30, further comprising a bus termination switching device which causes a termination of the wires of the two wire bus by means of impedances which are asymmetrical with respect to a ground input of the semiconductor circuit, when said semiconductor circuit is in the "SLEEP" mode.

34. Integrated semiconductor circuit according to claim 33, wherein

in the "NORMAL" mode, the bus termination switching device selectively connects first and second identical termination elements to the wires of the two wire bus;

and

in the "SLEEP" mode, the bus termination switching device connects at least a first alternate termination element integrated in the semiconductor circuit to a corresponding bus wire.

35. Integrated semiconductor circuit according to claim 34, wherein the identical termination elements are connected as external circuit elements discretely to the semiconductor circuit.

36. Integrated semiconductor circuit according to claim 34, wherein the first identical termination element and the alternate termination element are resistors, said first alternate termination element having a resistance which is much larger than a resistance of the first identical termination element.

37. Integrated semiconductor circuit according to claim 34, further comprising:

a bus fault recognition device which detects at least one bus fault which has an effect in the "SLEEP" operating mode, said bus fault recognition device causing the bus termination switching device to disconnect the first integrated alternate termination element, and to connect at least one second alternate termination element to the bus.

38. Integrated semiconductor element according to claim 37, wherein:

the second alternate termination element is dimensioned relative to the first integrated alternate termination element so that, in the case of a fault, a lower current flows through the second alternate termination element then flows through the first integrated alternate termination element in the absence of an error.

39. Integrated semiconductor circuit according to claim 30, further having at least one of two additional operating modes, a reception only RECEIVE ONLY mode, and a readiness STANDBY mode, in which either the current supply of the transmitting device can be switched off or the transmitting device can be disconnected from the bus.

40. Integrated semiconductor circuit according to claim 30, further comprising a device which blocks a current supply to the transmitting device as a function of detected faults.

41. Integrated semiconductor circuit according to claim 30, further comprising a device which blocks a current supply to the transmitting device in the "SLEEP" mode.

42. Integrated semiconductor circuit according to claim 30, further comprising a device which blocks a current supply to the transmitting device upon recognition of an intrinsic error of the semiconductor circuit.

43. Integrated semiconductor circuit according to claim 30, further comprising filter elements which are switched so that one of them is operative at least between one bus wire and a corresponding one of two inputs of the receiving device or the wakeup recognition device.

44. Integrated semiconductor circuit according to claim 30, further comprising at least one filter element which is connected between an input for a wakeup signal and a wakeup recognition device.