Interactive CAD apparatus for designing packaging of logic circuit design

• US 6,117,183 A
• Filed: 08/26/1997
• Issued: 09/12/2000
• Est. Priority Date: 01/08/1996
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Nishimura, Masaharu, Teranishi, Mieko, Iwakura, Yoshiyuki, Ariyama, Masato, Katsumata, Akira
• Primary Examiner(s): Lintz, Paul R.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/894,695
• Time in Patent Office: 1,113 Days
• Field of Search: 395/500.02, 395/500.03, 395/500.06, 395/500.07, 395/500.12, 395/500.11, 395/500.15, 395/500.4, 716/1, 716/2, 716/5, 716/6, 716/10, 716/11, 716/14
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined. The apparatus includes: a component moving unit, responsive to an operator'"'"'s instruction, for moving a component on a display screen where a component placement diagram is displayed; an associated path extraction unit for extracting a signal path associated with the component being moved by the component moving unit; a temporary position calculation unit for calculating temporary position data representing a placement position corresponding to the position of the component on the display screen at prescribed intervals of time when the component is being moved by the component moving unit; an associated path delay calculation unit for successively calculating delay values for the signal path extracted by the associated path extraction unit, based on the temporary position data calculated by the temporary position calculation unit; and an associated path delay display unit for successively displaying the delay values calculated by the associated path delay calculation unit.

Claims

1. An interactive CAD apparatus for logic circuit packaging design, comprising:

component moving means, responsive to an operator'"'"'s instruction, for moving a component on a display screen where a component placement diagram is displayed;

associated path extraction means for extracting a signal path associated with the component being moved by said component moving means;

temporary position calculation means for calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved by said component moving means;

associated path delay calculation means for successively calculating delay values for the signal path extracted by said associated path extraction means, based on the temporary position data calculated by said temporary position calculation means; and

associated path delay display means for successively displaying on said display screen the delay values calculated by said associated path delay calculation means.

3. An interactive CAD apparatus for logic circuit packaging design according to claim 1, wherein said associated path delay calculation means calculates the delay values in a simplified manner based on an increase or decrease in inter-component distance as said component is moved.

4. An interactive CAD apparatus for logic circuit packaging design according to claim 1, further comprising interconnection display means for displaying associated interconnections on the screen where said component placement diagram is displayed, by successively changing the way of displaying said interconnections depending on the magnitude of the delay values successively calculated by said associated path delay calculation means.

5. An interactive CAD apparatus for logic circuit packaging design according to claim 4, wherein said associated path delay calculation means calculates the delay values in a simplified manner based on an increase or decrease in inter-component distance as said component is moved.

6. An interactive CAD apparatus for logic circuit packaging design according to claim 4, further comprising interconnection display means for displaying associated interconnections on the screen where said component placement diagram is displayed, by successively changing the way of displaying said interconnections depending on the magnitude of the delay values successively calculated by said associated path delay calculation means.

2. An interactive CAD apparatus for logic circuit packaging design, comprising:

component moving means, responsive to an operator'"'"'s instruction, for moving a component on a display screen where a component placement diagram is displayed;

temporary position calculation means for calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved by said component moving means;

associated path delay calculation means for successively calculating delay values for a signal path specified by an operator, based on the temporary position data calculated by said temporary position calculation means; and

associated path delay display means for successively displaying on said display screen the delay values calculated by said associated path delay calculation means.

7. An interactive CAD apparatus for logic circuit packaging design, comprising:

component moving means, responsive to an operator'"'"'s instruction, for moving a component on a display screen where a component placement diagram is displayed, said component placement diagram being divided into a plurality of interconnection meshes;

associated path extraction means for extracting a signal path associated with the component being moved by said component moving means, said signal path being comprised of at least one interconnection route;

temporary position calculation means for calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved by said component moving means;

mesh pass count calculation means for calculating, based on the temporary position data calculated by said temporary position calculation means, the number of signal paths that pass across each interconnection mesh associated with an interconnection route of the signal path extracted by said associated path extraction means, the number of signal paths crossing each of said interconnection meshes determining a degree of interconnection crowdedness of each of said interconnection meshes; and

interconnection crowdedness map display means for successively displaying the degree of interconnection crowdedness of each interconnection mesh in the form of a map on said display screen in accordance with the magnitude of the number of signal paths calculated by said mesh pass count calculation means.

8. An interactive CAD apparatus for logic circuit packaging design according to claim 7, wherein said interconnection crowdedness map display means displays the interconnection crowdedness of each interconnection mesh in such a manner that the degree of the crowdedness is identifiable by a color assigned thereto.

10. A method according to claim 8, wherein the step of successively calculating delay values for said signal path calculates the delay values in a simplified manner based on an increase or decrease in inter-component distance as said component is moved.

11. A method according to claim 8, further comprising the step of displaying associated interconnections on the screen where said component placement diagram is displayed, by successively changing the way of displaying said interconnections depending on the magnitude of the delay values successively calculated in the step of successively calculating delay values for said signal path.

9. A method of displaying signal path delay values on a display screen in an interactive CAD apparatus for logic circuit packaging design, comprising the steps of:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) extracting a signal path associated with the component being moved in said step (a);

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) successively calculating delay values for the signal path extracted in said step (b), based on the temporary position data calculated in said step (c); and

(e) successively displaying on said display screen the delay values calculated in said step (d).

12. A method of displaying a channel pass count graph in real time on a display screen in an interactive CAD apparatus for logic circuit packaging design, comprising the steps of:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) extracting a signal path associated with the component being moved in said step (a), said signal path being comprised of at least one interconnection route;

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) displaying a plurality of horizontal and vertical interconnection channels on said component placement diagram, said interconnection routes passing across said interconnection channels;

(e) based on the temporary position data calculated in said step (c), calculating the number of signal paths that pass across each interconnection channel associated with an interconnection route of the signal path extracted in said step (b); and

(f) successively displaying on said display screen a channel pass count graph showing in the form of a graph the number of signal paths calculated in said step (e).

13. A method of displaying an interconnection crowdedness map in real time on a display screen in an interactive CAD apparatus for logic circuit packaging design, comprising the steps of:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed, said component placement diagram being divided into a plurality of interconnection meshes;

(b) extracting a signal path associated with the component being moved in said step (a), said signal path being comprised of at least one interconnection route;

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) based on the temporary position data calculated in said step (c), calculating the number of signal paths that pass across each interconnection mesh associated with an interconnection route of the signal path extracted in said step (b), the number of signal paths crossing each of said interconnection meshes determining a degree of interconnection crowdedness of each of said interconnection meshes; and

(e) successively displaying on said display screen an interconnection crowdedness map showing in the form of a map the degree of interconnection crowdedness of each interconnection mesh in accordance with the magnitude of the number of signal paths calculated in said step (d).

14. A method according to claim 13, wherein the step of displaying the interconnection crowdedness map displays the interconnection crowdedness of each interconnection mesh in such a manner that the degree of the crowdedness is identifiable by a color assigned thereto.

15. A program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for displaying signal path delay values on a display screen in an interactive CAD apparatus for logic circuit packaging design, said method steps comprising:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) extracting a signal path associated with the component being moved in said step (a);

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) successively calculating delay values for the signal path extracted in said step (b), based on the temporary position data calculated in said step (c); and

(e) successively displaying on said display screen the delay values calculated in said step (d).

16. A program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for displaying signal path delay values on a display screen in an interactive CAD apparatus for logic circuit packaging design, said method steps comprising:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(c) successively calculating delay values for a signal path specified by an operator, based on the temporary position data calculated in said step (b); and

(d) successively displaying on said display screen the delay values calculated in said step (c).

17. A program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for displaying a channel pass count graph in real time on a display screen in an interactive CAD apparatus for logic circuit packaging design, said method steps comprising:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) extracting a signal path associated with the component being moved in said step (a), said signal path being comprised of at least one interconnection route;

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) displaying a plurality of horizontal and vertical interconnection channels on said component placement diagram, said interconnection routes passing across said interconnection channels;

(e) based on the temporary position data calculated in said step (c), calculating the number of signal paths that pass across each interconnection channel associated with an interconnection route of the signal path extracted in said step (b); and

(f) successively displaying on said display screen a channel pass count graph showing in the form of a graph the number of signal paths calculated in said step (e).

18. A program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for displaying an interconnection crowdedness map in real time on a display screen in an interactive CAD apparatus for logic circuit packaging design, said method steps comprising:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed, said component placement diagram being divided into a plurality of interconnection meshes;

(b) extracting a signal path associated with the component being moved in said step (a), said signal path being comprised of at least one interconnection route;

(c) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(d) based on the temporary position data calculated in said step (c), calculating the number of signal paths that pass across each interconnection mesh associated with an interconnection route of the signal path extracted in said step (b), the number of signal paths crossing each of said interconnection meshes determining a degree of interconnection crowdedness of each of said interconnection meshes; and

(e) successively displaying on said display screen an interconnection crowdedness map showing in the form of a map the degree of interconnection crowdedness of each interconnection mesh in accordance with the magnitude of the number of signal paths calculated in said step (d).

19. An interactive CAD apparatus for logic circuit packaging design, comprising:

component moving means, responsive to an operator'"'"'s instruction, for moving a component on a display screen where a component placement diagram is displayed;

associated path extraction means for extracting a signal path associated with the component being moved by said component moving means, said signal path being comprised of at least one interconnection route;

temporary position calculation means for calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved by said component moving means;

a plurality of horizontal and vertical interconnection channels displayed on said component placement diagram, said interconnection routes passing across said interconnection channels;

channel pass count calculation means for calculating, based on the temporary position data calculated by said temporary position calculation means, the number of signal paths that pass across each interconnection channel associated with an interconnection route of the signal path extracted by said associated path extraction means; and

channel pass count display means for successively displaying the number of signal paths calculated by said channel pass count calculation means in the form of a graph on said display screen.

20. A method of displaying signal path delay values on a display screen in an interactive CAD apparatus for logic circuit packaging design, comprising the steps of:

(a) moving a component, in response to an operator'"'"'s instruction, on the display screen where a component placement diagram is displayed;

(b) calculating temporary position data representing a placement position corresponding to the position of said component on said display screen at prescribed intervals of time when said component is being moved in said step (a);

(c) successively calculating delay values for a signal path specified by an operator, based on the temporary position data calculated in said step (b); and

(d) successively displaying on said display screen the delay values calculated in said step (c).

21. A method according to claim 20, wherein the step of successively calculating delay values for said signal path calculates the delay values in a simplified manner based on an increase or decrease in inter-component distance as said component is moved.

22. A method according to claim 20, further comprising the step of displaying associated interconnections on the screen where said component placement diagram is displayed, by successively changing the way of displaying said interconnections depending on the magnitude of the delay values successively calculated in the step of successively calculating delay values for said signal path.

23. A method of displaying signal path delay values on a display screen comprising:

calculating temporary position data at prescribed intervals of time representing a placement position corresponding to the position of a component being moved within a component placement diagram on the display screen;

successively calculating delay values for a signal path based on the calculated temporary position data; and

successively displaying on the display screen the calculated delay values.

24. A method of displaying a channel pass count graph in real time on a display screen comprising:

calculating temporary position data at prescribed intervals of time representing a placement position corresponding to the position of a component being moved within a component placement diagram on the display screen, the component having an associated signal path specified by an operator and comprised of at least one interconnection route, and the component placement diagram having a plurality of interconnection channels;

based on the temporary position data, calculating the number of signal paths that pass across each interconnection channel associated with the interconnection route; and

successively displaying on the display screen the channel pass count graph showing the calculated number of signal paths.

25. A method of displaying an interconnection crowdedness map in real time on a display screen comprising:

calculating temporary position data at prescribed intervals of time representing a placement position corresponding to the position of a component being moved within a component placement diagram on the display screen, the component having an associated signal path specified by an operator and comprised of at least one interconnection route, and the component placement diagram being divided into a plurality of interconnection meshes;

based on the temporary position data, calculating the number of signal paths that pass across each interconnection mesh associated with the interconnection route, the number of signal paths crossing each of the interconnection meshes determining a degree of interconnection crowdedness of each of the interconnection meshes; and

successively displaying on the display screen the interconnection crowdedness map showing the degree of interconnection crowdedness of each interconnection mesh in accordance with the magnitude of the calculated number of signal paths.