Stackable layers containing encapsulated chips

• US 6,117,704 A
• Filed: 03/31/1999
• Issued: 09/12/2000
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Ozguz, Volkan H., Camien, Andrew N., Yamaguchi, James S.
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US09/282,704
• Time in Patent Office: 531 Days
• Field of Search: 438/106, 438/110, 438/113, 438/127, 438/460
• US Class Current: 438/100
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.

Claims

1. A method of preparing a plurality of pre-formed IC chips for encapsulation in stackable layers of an electronic package, comprising the following steps;

forming a neo-wafer structure having a flat surface;

photo-patterning and processing the flat surface to precisely locate and form vias in the flat surface;

providing a plurality of IC chips, each having conductive bumps connected to the terminals of the IC chip;

inserting the conductive bumps of the IC chips through the vias in the flat neo-wafer surface, in order to precisely locate the chips with respect to one another, and in order to expose the conductive bumps to suitable electrical connections on the other side of the flat neo-wafer surface from the IC chips;

covering the chips in the neo-wafer with non-conductive encapsulating material which supports the chips; and

dicing the neo-wafer to provide a plurality of separate stackable layers, each having the same area and each containing at least one encapsulated chip.

2. The method of claim 1 in which;

the neo-wafer structure is formed with a plurality of separate chambers next to the flat surface;

the vias formed in the flat surface of the neo-wafer open into the respective chambers; and

the non-conductive encapsulating material in the neo-wafer is separated into a plurality of separate segments by the chambers formed in the neo-wafer.

3. The method of claim 1 in which the IC chips each are pre-formed by a wafering process, diced into separate chips, and pre-tested to provide known-good chips for insertion in the neo-wafer.

4. The method of claim 2 in which the IC chips each are pre-formed by a wafering process, diced into separate chips, and pre-tested to provide known-good chips for insertion in the neo-wafer.

5. The method of claim 3 in which the neo-wafer comprises two sub-assemblies:

a flat sub-assembly formed as a supporting plate carrying a layer of dielectric material developable by photo-lithography; and

a frame-like sub-assembly having a plurality of open chambers formed therein by chamber-defining walls.

6. The method of claim 4 in which the neo-wafer comprises two sub-assemblies:

a flat sub-assembly formed as a supporting plate carrying a layer of dielectric material developable by photo-lithography; and

a frame-like sub-assembly having a plurality of open chambers formed therein by chamber-defining walls.

7. The method of claim 3 in which:

dielectric material is applied to the flat-neo-wafer surface to cover the conductive bumps;

vias are formed in the dielectric material to expose the conductive bumps;

electrical conductors are formed on top of the dielectric material, which conductors (a) are connected to the conductive bumps, and (b) lead to one or more edges of the respective encapsulated IC chips; and

dielectric material is applied over the electrical conductors.

8. The method of claim 4 in which:

dielectric material is applied to the flat-neo-wafer surface to cover the conductive bumps;

vias are formed in the dielectric material to expose the conductive bumps;

electrical conductors are formed on top of the dielectric material, which conductors (a) are connected to the conductive bumps, and (b) lead to one or more edges of the respective encapsulated IC chips; and

dielectric material is applied over the electrical conductors.

9. The method of claim 5 in which:

dielectric material is applied to the flat-neo-wafer surface to cover the conductive bumps;

vias are formed in the dielectric material to expose the conductive bumps;

electrical conductors are formed on top of the dielectric material, which conductors (a) are connected to the conductive bumps, and (b) lead to one or more edges of the respective encapsulated IC chips; and

dielectric material is applied over the electrical conductors.

10. The method of claim 6 in which:

dielectric material is applied to the flat-neo-wafer surface to cover the conductive bumps;

vias are formed in the dielectric material to expose the conductive bumps;

electrical conductors are formed on top of the dielectric material, which conductors (a) are connected to the conductive bumps, and (b) lead to one or more edges of the respective encapsulated IC chips; and

dielectric material is applied over the electrical conductors.

11. A method of preparing a plurality of pre-formed chips for encapsulation in stackable layers of a multi-chip package, comprising the following steps;

forming a neo-wafer structure having a flat surface;

processing the flat surface to precisely locate and form vias in the flat surface;

providing a plurality of chips, each having signal-carrying bumps connected to the terminals of the chip;

inserting the bumps of the chips through the vias in the flat neo-wafer surface, in order to precisely locate the chips with respect to one another, and in order to expose the bumps to suitable connections on the other side of the flat neo-wafer surface from the chips;

covering the chips in the neo-wafer with non-conductive encapsulating material which supports the chips; and

dicing the neo-wafer to provide a plurality of separate stackable layers, each having the same area and each containing at least one encapsulated chip.

12. The method of claim 11 in which;

the neo-wafer structure is formed with a plurality of separate chambers next to the flat surface;

the vias formed in the flat surface of the neo-wafer open into the respective chambers; and

the non-conductive encapsulating material in the neo-wafer is separated into a plurality of separate segments by the chambers formed in the neo-wafer.

13. The method of claim 11 in which the chips each are pre-formed by a wafering process, diced into separate chips, and pre-tested before insertion in the neo-wafer.

14. The method of claim 12 in which the chips each are pre-formed by a wafering process, diced into separate chips, and pre-tested before insertion in the neo-wafer.

15. The method of claim 12 in which the neo-wafer comprises two sub-assemblies:

a flat sub-assembly formed as a supporting plate carrying a layer of non-conductive material; and

a frame-like sub-assembly having a plurality of open chambers formed therein by chamber-defining walls.