Stackable layers containing encapsulated chips
First Claim
1. A method of preparing a plurality of pre-formed IC chips for encapsulation in stackable layers of an electronic package, comprising the following steps;
- forming a neo-wafer structure having a flat surface;
photo-patterning and processing the flat surface to precisely locate and form vias in the flat surface;
providing a plurality of IC chips, each having conductive bumps connected to the terminals of the IC chip;
inserting the conductive bumps of the IC chips through the vias in the flat neo-wafer surface, in order to precisely locate the chips with respect to one another, and in order to expose the conductive bumps to suitable electrical connections on the other side of the flat neo-wafer surface from the IC chips;
covering the chips in the neo-wafer with non-conductive encapsulating material which supports the chips; and
dicing the neo-wafer to provide a plurality of separate stackable layers, each having the same area and each containing at least one encapsulated chip.
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Accused Products
Abstract
A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.
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Citations
15 Claims
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1. A method of preparing a plurality of pre-formed IC chips for encapsulation in stackable layers of an electronic package, comprising the following steps;
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forming a neo-wafer structure having a flat surface; photo-patterning and processing the flat surface to precisely locate and form vias in the flat surface; providing a plurality of IC chips, each having conductive bumps connected to the terminals of the IC chip; inserting the conductive bumps of the IC chips through the vias in the flat neo-wafer surface, in order to precisely locate the chips with respect to one another, and in order to expose the conductive bumps to suitable electrical connections on the other side of the flat neo-wafer surface from the IC chips; covering the chips in the neo-wafer with non-conductive encapsulating material which supports the chips; and dicing the neo-wafer to provide a plurality of separate stackable layers, each having the same area and each containing at least one encapsulated chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of preparing a plurality of pre-formed chips for encapsulation in stackable layers of a multi-chip package, comprising the following steps;
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forming a neo-wafer structure having a flat surface; processing the flat surface to precisely locate and form vias in the flat surface; providing a plurality of chips, each having signal-carrying bumps connected to the terminals of the chip; inserting the bumps of the chips through the vias in the flat neo-wafer surface, in order to precisely locate the chips with respect to one another, and in order to expose the bumps to suitable connections on the other side of the flat neo-wafer surface from the chips; covering the chips in the neo-wafer with non-conductive encapsulating material which supports the chips; and dicing the neo-wafer to provide a plurality of separate stackable layers, each having the same area and each containing at least one encapsulated chip. - View Dependent Claims (12, 13, 14, 15)
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Specification