Poly tip formation and self-align source process for split-gate flash cell
First Claim
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1. A method of forming a poly tip and a self-aligned source line split-gate flash memory cell comprising the steps of:
- providing a semiconductor substrate having active and passive regions defined;
forming a gate oxide layer over said substrate;
forming a first polysilicon layer over said gate oxide layer;
forming a first nitride layer over said first polysilicon layer (poly-1);
forming a shallow trench ST-photomask over said first nitride layer;
forming a shallow trench in said substrate by etching said first nitride layer, first polysilicon layer, gate oxide layer and said substrate;
removing said ST-photomask;
depositing a first oxide layer over said substrate including said shallow trench;
performing chemical mechanical polishing of said first oxide layer;
removing said first nitride layer;
depositing a second nitride layer;
forming a second oxide layer over said second nitride layer;
forming a poly-1 photomask over said second oxide layer;
forming openings in underlying said second oxide layer, said second nitride layer and first polysilicon layer through patterns in said poly-1 photomask to form a floating gate structure;
forming a self-aligned source SAS-photomask over said poly1 photomask;
etching through said SAS-photomask;
removing said SAS-photomask;
partial etching said second nitride layer to form a notch on an edge of said second nitride layer thus exposing a edge portion of said floating gate structure followed by oxidizing said ledge portion and sidewalls of said floating gate structure to form a sharp poly tip therebetween;
forming a hot temperature oxide (HTO) layer over said substrate including said floating gate structure;
forming a second polysilicon layer (poly-2) over said HTO layer;
forming a poly-2 photomask over said second polysilicon layer;
etching and patterning said second polysilicon layer through said poly-2 photomask to form a control gate;
performing ion implantation through said patterning in said second polysilicon layer to form source regions in said substrate;
removing said poly-2 photomask;
forming a conformal oxide layer over said substrate;
forming oxide spacers;
performing ion implantation to form drain regions in said substrate;
forming interlevel dielectric layer over said substrate;
forming contact holes in said interlevel dielectric layer;
forming metal in said contact holes; and
etching back excess metal over said substrate in preparation for performing remaining process steps in manufacturing said split-gate flash memory cell.
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Abstract
A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon/nitride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.
86 Citations
32 Claims
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1. A method of forming a poly tip and a self-aligned source line split-gate flash memory cell comprising the steps of:
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providing a semiconductor substrate having active and passive regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a first nitride layer over said first polysilicon layer (poly-1); forming a shallow trench ST-photomask over said first nitride layer; forming a shallow trench in said substrate by etching said first nitride layer, first polysilicon layer, gate oxide layer and said substrate; removing said ST-photomask; depositing a first oxide layer over said substrate including said shallow trench; performing chemical mechanical polishing of said first oxide layer; removing said first nitride layer; depositing a second nitride layer; forming a second oxide layer over said second nitride layer; forming a poly-1 photomask over said second oxide layer; forming openings in underlying said second oxide layer, said second nitride layer and first polysilicon layer through patterns in said poly-1 photomask to form a floating gate structure; forming a self-aligned source SAS-photomask over said poly1 photomask; etching through said SAS-photomask; removing said SAS-photomask; partial etching said second nitride layer to form a notch on an edge of said second nitride layer thus exposing a edge portion of said floating gate structure followed by oxidizing said ledge portion and sidewalls of said floating gate structure to form a sharp poly tip therebetween; forming a hot temperature oxide (HTO) layer over said substrate including said floating gate structure; forming a second polysilicon layer (poly-2) over said HTO layer; forming a poly-2 photomask over said second polysilicon layer; etching and patterning said second polysilicon layer through said poly-2 photomask to form a control gate; performing ion implantation through said patterning in said second polysilicon layer to form source regions in said substrate; removing said poly-2 photomask; forming a conformal oxide layer over said substrate; forming oxide spacers; performing ion implantation to form drain regions in said substrate; forming interlevel dielectric layer over said substrate; forming contact holes in said interlevel dielectric layer; forming metal in said contact holes; and etching back excess metal over said substrate in preparation for performing remaining process steps in manufacturing said split-gate flash memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsSung, Hung-Cheng, Hsieh, Chia-Ta, Kuo, Di-Son, Lin, Yai-Fen
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)MALSAWMA, LALRINFAMKIM HMAR
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Application NumberUS09/193,670Time in Patent Office665 DaysField of Search438/151, 438/197, 438/257, 438/264, 438/265, 438/279, 438/299, 257/288, 257/314, 257/315, 257/316, 257/317, 257/321US Class Current438/265CPC Class CodesH01L 29/42324 Gate electrodes for transis...H10B 41/10 characterised by the top-vi...H10B 41/30 characterised by the memory...
