Input/output protection circuit having an SOI structure

• US 6,118,154 A
• Filed: 10/08/1997
• Issued: 09/12/2000
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamaguchi, Yasuo, Inoue, Yasuo, Sato, Hirotoshi, Iwamatsu, Toshiaki
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/947,345
• Time in Patent Office: 1,070 Days
• Field of Search: 257/360, 257/361, 257/356, 257/357
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

Claims

1. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit including a plurality of MOS transistors, said I/O protection circuit comprising a first MOS element including:

a first semiconductor film formed on said insulating layer and connected between said terminal and a first power supply line;

a first gate insulating film formed on said first semiconductor film;

a first floating gate electrode formed on said first gate insulating film;

said first semiconductor film including;

a substrate region of a first conductivity type located under said first floating gate electrode;

a first conductive region of a second conductivity type neighboring to one side of said substrate region and connected to said first power supply line; and

a second conductive region of the second conductivity type neighboring to the other side of said substrate region and connected to said terminal;

wherein

said plurality of MOS transistors include a substrate region having a first impurity concentration, and

said substrate region of said first MOS element has a second impurity concentration higher than said first impurity concentration.

2. The I/O protection circuit according to claim 1, wherein

said first semiconductor film includes:

a substrate region of a first conductivity type located under said first gate electrode;

a first conductive region of a second conductivity type neighboring to one side of said substrate region and connected to said first power supply line; and

a second conductive region of the second conductivity type neighboring to the other side of said substrate region and connected to said terminal.

3. The I/O protection circuit according to claim 2, wherein said substrate region of said first MOS element is floated.

4. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit including a plurality of MOS transistors, said I/O protection circuit comprising a first MOS element including:

a first semiconductor film formed on said insulating layer and connected between said terminal and a first power supply line;

a first gate insulating film formed on said first semiconductor film;

a first floating gate electrode formed on said first gate insulating film;

said first semiconductor film including;

a substrate region of a first conductivity type located under said first floating gate electrode;

a first conductive region of a second conductivity type neighboring to one side of said substrate region and connected to said first power supply line; and

a second conductive region of the second conductivity type neighboring to the other side of said substrate region and connected to said terminal;

wherein

said plurality of MOS transistors are of the second conductivity type, and have gate electrodes made of polycrystalline silicon of the second conductivity type, and

said first gate electrode of said first MOS element is made of polycrystalline silicon of the first conductivity type.

5. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit including a plurality of MOS transistors, said I/O protection circuit comprising a first MOS element including:

a first semiconductor film formed on said insulating layer and connected between said terminal and a first power supply line;

a first gate insulating film formed on said first semiconductor film; and

a first floating gate electrode formed on said first gate insulating film;

wherein

said first semiconductor film includes;

a first conductive region of the first conductivity type located under said first gate electrode,

a second conductive region of the first conductivity type neighboring to one side of said first conductive region and connected to said first power supply line, and

a third conductive region of the second conductivity type neighboring to the other side of said first conductive region and connected to said terminal.

6. The I/O protection circuit according to claim 5, wherein

said plurality of MOS transistors include a substrate region having a first impurity concentration, and

said first conductive region of said first MOS element has a second impurity concentration higher than said first impurity concentration.

7. The I/O protection circuit according to claim 5, wherein

said plurality of MOS transistors are of the second conductivity type, and have gate electrodes made of polycrystalline silicon of the second conductivity type, and

said first gate electrode of said first MOS element is made of polycrystalline silicon of the first conductivity type.

8. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit including a plurality of MOS transistors isolated from each other by a field shield method, and said I/O protection circuit comprising an MOS element including:

a semiconductor film formed on said insulating layer and connected between said terminal and a power supply line;

a gate insulating film formed on said semiconductor film; and

a gate electrode formed on said gate insulating film and in the same layer as a gate electrode provided for a field shield method.

9. The I/O protection circuit according to claim 8, wherein

said semiconductor film includes:

a substrate region of a first conductivity type located under said gate electrode;

a first conductive region of a second conductivity type neighboring to one side of said substrate region and connected to said power supply line; and

a second conductive region of the second conductivity type neighboring to the other side of said substrate region and connected to said terminal.

10. The I/O protection circuit according to claim 9, wherein

said plurality of MOS transistors include a substrate region having a first impurity concentration, and

said substrate region of said MOS element has a second impurity concentration higher than said first impurity concentration.

11. The I/O protection circuit according to claim 9, wherein

said substrate region of said MOS element is floated.

12. The I/O protection circuit according to claim 9, wherein

said plurality of MOS transistors are of the second conductivity type, and have gate electrodes made of polycrystalline silicon of the second conductivity type, and

said gate electrode of said MOS element is made of polycrystalline silicon of the first conductivity type.

13. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit, said I/O protection circuit comprising:

a semiconductor film of a first conductivity type formed on said insulating layer;

a plurality of first conductive regions of the first conductivity type formed in said semiconductor film and connected to said terminal; and

a plurality of second conductive regions of a second conductivity type formed in said semiconductor film and connected to a power supply line.

14. The I/O protection circuit according to claim 13, wherein

said first and second conductive regions are disposed in a matrix form, and are disposed alternately to each other in each of rows and columns in said matrix.

15. The I/O protection circuit according to claim 13, wherein

round interfaces are formed between said semiconductor film and said first and second conductive regions.

16. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit including a MOS transistor having a source/drain region connected to an interconnection through a first contact hole formed in an insulating film formed on said insulating layer, said I/O protection circuit comprising:

a semiconductor substrate of a first conductivity type having a main surface on which said insulating layer is formed, said semiconductor substrate connected to a power supply node; and

a conductive region of a second conductivity type formed at said main surface of said semiconductor substrate and connected to said terminal through a second contact hole formed in said insulating layer and said insulating film.

17. The I/O protection circuit according to claim 16, wherein

said first conductivity type is p-type, and said power supply node is a ground node.

18. An I/O protection circuit formed on an insulating layer and connected between a terminal and an internal circuit, said I/O protection circuit comprising:

a first conductive region of a first conductivity type formed on said insulating layer and connected to a first power supply line;

a first insulating film formed on said first conductive region and having a first contact hole extending to said first conductive region; and

a first conductive film of a second conductivity type formed on said first insulating film, in contact with said first conductive region through said first contact hole and connected to said terminal.

19. The I/O protection circuit according to claim 18, further comprising:

a second conductive region of the second conductivity type formed on said insulating layer and connected to a second power supply line;

a second insulating film formed on said second conductive region and having a second contact hole extending to said second conductive region; and

a second conductive film of the first conductivity type formed on said second insulating film, in contact with said second conductive region through said second contact hole and connected to said terminal.

20. A protection circuit formed on an insulating layer and connected between a terminal and an internal circuit, said protection circuit comprising:

a semiconductor film formed on said insulting layer;

a plurality of first conductive regions of a first conductivity type formed in said semiconductor film and connected to said terminal; and

a plurality of second conductive regions of a second conductivity type formed in said semiconductor film and connected to a power supply line, wherein

said first and second conductive regions are disposed in a matrix form, and are disposed alternately to each other in each of rows and columns in said matrix.

21. A protection circuit formed on an insulating layer and connected between a terminal and an internal circuit, said protection circuit comprising:

a semiconductor film formed on said insulating layer;

a plurality of first conductive regions of a first conductivity type formed in said semiconductor film and connected to said terminal; and

a plurality of second conductive regions of a second conductivity type formed in said semiconductor film and connected to a power supply line, wherein round iterfaces are formed between said semiconductor film and said first and second conductive regions.