Semiconductor die metal layout for flip chip packaging

• US 6,118,180 A
• Filed: 11/03/1997
• Issued: 09/12/2000
• Est. Priority Date: 11/03/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Liang, Mike T., Rao, Ramoji K., Loo, Mike C.
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US08/963,553
• Time in Patent Office: 1,044 Days
• Field of Search: 257/737, 257/738, 257/778, 257/780, 257/781, 257/782, 257/784, 228/180.22, 438/613, 438/622, 438/626, 438/61
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/20106 : Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K

Abstract

Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Claims

1. A metal layout on a semiconductor die, comprising:

a surface metal bonding pad;

a metal region adjacent to said pad and spaced between about 1.0 and 3.0 μ

m from said pad; and

an under bump metal pad overlying said surface metal pad and at least a portion of said adjacent metal region, and connected to said surface metal pad through a via.

2. The metal layout of claim 1, wherein said adjacent metal region comprises a metal trace.

3. The metal layout of claim 1, wherein said adjacent metal region comprises dummy metal.

4. The metal layout of claim 1, further comprising a solder ball attached to said under bump metal pad.

5. The metal layout of claim 1, further comprising a dielectric layer deposited over said surface metal pad and adjacent metal region.

6. The metal layout of claim 1, wherein said surface metal pad is between about 55 and 90 μ

m at its maximum extent.

7. The metal layout of claim 1, wherein said metal region adjacent to said pad is spaced between about 1.5 and 2.5 μ

m from said pad.

8. The metal layout of claim 1, wherein said metal region adjacent to said pad is spaced about 2.0 μ

m from said pad.

9. The metal layout of claim 1, wherein said adjacent metal region comprises one or more metal traces and one or more dummy metal regions.

10. The metal layout of claim 1, wherein said pad forms part of a row having a pitch of less than about 250 μ

m.

11. The metal layout of claim 1, wherein said semiconductor die comprises transistors having about a 0.25 μ

m gate width.

12. The metal layout of claim 6, wherein said surface metal pad is between about 60 and 90 μ

m at its maximum extent.

13. The metal layout of claim 12, wherein said surface metal pad is about 80 μ

m at its maximum extent.

14. The metal layout of claim 9, wherein each of said traces and dummy metal regions are separated from each other by between about 1.0 and 3.0 μ

m.

15. The metal layout of claim 10, wherein said pad forms part of a row having a pitch of about 200 μ

m.

16. A metal layout on a semiconductor die, comprising:

a surface metal bonding pad;

means adjacent to said pad and spaced between about 1.0 and 3.0 μ

m from said pad for supporting an under bump metal pad; and

an under bump metal pad overlying said surface metal pad and at least a portion of said supporting means, and connected to said surface metal pad through a via.

17. A metal layout on a semiconductor die, comprising:

a surface metal bonding pad;

a metal region laterally adjacent to and spaced apart from said surface metal pad, said adjacent metal region;

a solder ball-supporting under bump metal pad overlying said surface metal pad and at least a portion of said adjacent metal region, said under bump metal pad separated from said surface metal pad and said adjacent metal region by only a single layer of dielectric, and connected to said surface metal pad through a via.

18. The metal layout of claim 17, wherein said adjacent metal region comprises a metal trace.

19. The metal layout of claim 17, wherein said adjacent metal region comprises dummy metal.

20. The metal layout of claim 17, wherein said layer comprises a dielectric layer deposited over said surface metal pad and adjacent metal region.

21. The metal layout of claim 17, wherein the spacing between the surface metal pad and the adjacent metal region is between about 1.0 and 3.0 μ

m.