System and method for bonding wafers

• US 6,118,181 A
• Filed: 07/29/1998
• Issued: 09/12/2000
• Est. Priority Date: 07/29/1998
• Status: Expired due to Term

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Hoen, Storrs, Merchant, Paul P.
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US09/124,099
• Time in Patent Office: 776 Days
• Field of Search: 438/455, 438/648, 438/109, 438/456, 257/750, 257/754, 257/766, 257/777
• US Class Current: 257/757
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.

Claims

1. A micromachined system, comprising:

a first wafer having a contact consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said chromium attached directly to said palladium; and

a second wafer having silicon on at least one surface, said silicon bonded with said palladium to form a bond between said first wafer and said second wafer.

2. The system of claim 1, wherein said first and second wafers include complementary metal-oxide semiconductor (CMOS) circuitry and said bond forms an electrical connection between said CMOS circuitry of said first wafer and said CMOS circuitry of said second wafer.

3. The system of claim 1, wherein said bond is formed at temperatures less than 500 degrees Celsius.

4. A system, comprising:

a first micromachined wafer having a first layer consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said first layer attached directly to said adhesive layer and

a second micromachined wafer having a second layer including silicon, said second layer configured to engage said first layer and to form a bond between said first layer and said second layer when said layers are heated to a bonding temperature,

wherein said bond between said first layer and said second layer is sufficient to maintain an alignment of said first wafer with respect to said second wafer and wherein said bond is configured to form an electrical connection between circuitry contained in said first wafer and circuitry contained in said second wafer.

5. The system of claim 4, wherein said circuitry contained in said first wafer and said circuitry contained in said second wafer are both complementary metal-oxide semiconductor (CMOS) circuitry.

6. The system of claim 4, wherein said bond between said first layer and said second layer is formed at temperatures less than 500 degrees Celsius.