Methods and apparatus for load sharing between parallel inverters in an AC power supply

• US 6,118,680 A
• Filed: 05/28/1999
• Issued: 09/12/2000
• Est. Priority Date: 05/28/1999
• Status: Expired due to Term

• Current Assignee: PECO II, Inc. (GE Aerospace)
• Original Assignee: Peco II
• Inventors: Roller, John, Karnes, Jon Drew, Mantov, Gueorgui I., Wallace, Kenneth Andrew
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/322,726
• Time in Patent Office: 473 Days
• Field of Search: 363/71, 363/16, 363/131, 363/123
• US Class Current: 363/71
• CPC Class Codes: G06F 1/0342 for generating simultaneously two or more related waveforms, e.g. with different phase angles only
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

Methods and apparatus are disclosed for achieving load balance between parallel inverters in an AC power supply. Load balancing reduces undesirable cross conduction current between the parallel inverters. Load balancing and the resulting reduction in cross conduction current are achieved without the need for common control circuitry between the parallel inverters. Thus, the single-fault protection offered by redundant parallel inverters is not compromised by the disclosed load balancing techniques.

Claims

1. For use with a system for supplying AC power to a load via a bus, the system developing a bus voltage on the bus and including first and second inverters, the first and second inverters being connected in parallel and operating at substantially the same frequency, a control circuit associated with the first inverter for reducing cross conduction current between the first and second inverters, the control circuit comprising:

a phase detector for developing a difference signal proportional to a difference between an input signal representative of an output current of the first inverter and a reference signal;

a filter cooperating with the phase detector for smoothing and sampling the difference signal; and

a signal generating circuit for adjusting the phase of an output voltage of the first inverter, the phase of the output voltage being dependent upon the difference signal, the signal generating circuit developing the reference signal, the reference signal being substantially representative of the output voltage of the first inverter but approximately 90 degrees out of phase with the output voltage, wherein the phase detector, the filter, and the signal generating circuit cooperate to match the phase of the output voltage of the first inverter to the phase of the output voltage of the second inverter to thereby reduce cross conduction current flowing between the first and second inverters.

2. A control circuit as defined in claim 1 further comprising a controlled switch coupled to the phase detector for delivering the input signal thereto.

3. A control circuit as defined in claim 2 wherein the controlled switch has a first state wherein the input signal delivered to the phase detector is representative of the bus voltage, and a second state wherein the input signal delivered to the phase detector is representative of the output current developed by the first inverter.

4. A control circuit as defined in claim 3 wherein, when the controlled switch is in the second state, the phase detector, the filter and the signal generating circuit cooperate to reduce cross conduction current flowing between the first and second inverters.

5. A control circuit as defined in claim 3 wherein, when the controlled switch is in the first state, the phase detector, the filter, and the signal generating circuit cooperate to substantially match the phase of the output voltage of the first inverter to the phase of the bus voltage.

6. A control circuit as defined in claim 1 wherein the phase detector comprises a multiplier.

7. A control circuit as defined in claim 1 wherein the filter comprises a resettable integrator for developing an average difference signal over a first predetermined time period.

8. A control circuit as defined in claim 1 wherein the signal generating circuit comprises a voltage controlled oscillator for developing a phase correcting signal and the reference signal.

9. A control circuit as defined in claim 8 further comprising an isolator in communication with the signal generating circuit for selectively preventing the output voltage of the first inverter from reaching the bus until the bus voltage and the output voltage of the first inverter are substantially in phase.

10. A control circuit as defined in claim 9 wherein the voltage controlled oscillator comprises a microcontroller coupled to the isolator, and the microcontroller controls the isolator to connect the output voltage of the first inverter to the bus when the average difference signal remains substantially constant for a second predetermined time period.

11. A control circuit as defined in claim 10 further comprising a controlled switch coupled to the phase detector for delivering the input signal thereto, the controlled switch having a first state wherein the input signal delivered to the phase detector is representative of the bus voltage, and a second state wherein the input signal delivered to the phase detector is representative of the output current developed by the first inverter, the microcontroller being coupled to the controlled switch for switching the controlled switch between the first and the second states.

12. A control circuit as defined in claim 1 further comprising means for matching an amplitude of the output voltage of the first inverter and an amplitude of an output voltage of the second inverter.

13. A control circuit as defined in claim 12 wherein the matching means comprises a current sense resistor coupled to the first inverter to cause a decrease in the output voltage of the first inverter in response to an increase in load current.

23. A control circuit as defined in claim 1 wherein the cross conduction current flowing between the first and second inverters is reduced without employing common control circuitry between the first and second inverters.

27. A control circuit as defined in claim 1 wherein the second inverter is provided with a second control circuit comprising:

a second phase detector for developing a second difference signal proportional to a second difference between a second input signal representative of an output current of the second inverter and a second reference signal;

a second filter cooperating with the second phase detector for smoothing and sampling the second difference signal; and

a second signal generating circuit for adjusting the phase of an output voltage of the second inverter, the phase of the output voltage of the second inverter being dependent upon the second difference signal, the second signal generating circuit developing the second reference signal, the second reference signal being substantially representative of the output voltage of the second inverter but approximately 90 degrees out of phase with the output voltage of the second inverter, wherein the second phase detector, the second filter, and the second signal generating circuit cooperate to match the phase of the output voltage of the second inverter to the phase of the output voltage of the first inverter to thereby reduce cross conduction current flowing between the first and second inverters.

14. A system for supplying power to a load via a bus, the system comprising:

a first inverter coupled to the bus and developing a first output voltage and a first output current;

a second inverter coupled to the bus in parallel with the first inverter; and

a control circuit associated with the first inverter, the control circuit including a phase detector to detect a phase difference between the first output current and the first output voltage and a controlled oscillator adjusting the phase of the first output voltage based upon the detected phase difference, the phase detector being disposed in a phase locked loop with the controlled oscillator to reduce the detected phase difference to thereby reduce a quadrature current flowing between the first and second inverters.

15. A system as defined in claim 14 further comprising a second control circuit associated with the second inverter, the second control circuit including:

(1) a second phase detector to detect a phase difference between a second output current associated with the second inverter and a second output voltage associated with the second inverter and (2) a second controlled oscillator adjusting the phase of the second output voltage based upon the phase difference detected by the second phase detector, the second phase detector being disposed in a second phase locked loop with the second controlled oscillator to reduce the phase difference detected by the second phase detector to thereby reduce the quadrature current flowing between the first and second inverters.

16. A system as defined in claim 14 further comprising means for matching an amplitude of the output voltage of the first inverter and an amplitude of an output voltage of the second inverter.

17. A system as defined in claim 16 wherein the matching means comprises a first current sense resistor coupled to the first inverter to cause a decrease in the output voltage of the first inverter in response to an increase in load current and a second current sense resistor coupled to the second inverter to cause a decrease in the output voltage of the second inverter in response to an increase in the load current.

24. A system as defined in claim 14 wherein the quadrature current flowing between the first and second inverters is reduced without employing common control circuitry between the first and second inverters.

18. For use with a system for supplying power to a load via a bus, the system developing a bus voltage on the bus and including first and second inverters, the first and second inverters being connected in parallel and operating at substantially the same frequency, a control circuit associated with the first inverter comprising:

a controlled switch having a first state and a second state; and

a phase locked loop having an input coupled to the controlled switch such that, when the controlled switch is in the first state, the phase locked loop compares a signal representative of the bus voltage to a reference signal derived from an output voltage of the first inverter to drive the output voltage of the first inverter into substantial phase with the bus voltage, and, when the controlled switch is in the second state, the phase locked loop compares a signal derived from an output current of the first inverter to the reference signal derived from the output voltage of the first inverter to reduce a cross conduction current flowing between the first and second inverters.

19. A control circuit as defined in claim 18 wherein the cross conduction current has a quadrature component and the phase locked loop reduces the quadrature component of the cross conduction current.

25. A control circuit as defined in claim 18 wherein the cross conduction current flowing between the first and second inverters is reduced without employing common control circuitry between the first and second inverters.

28. A control circuit as defined in claim 18 wherein the second inverter is provided with a second control circuit comprising:

a second controlled switch having a first state and a second state; and

a second phase locked loop having an input coupled to the second controlled switch such that, when the second controlled switch is in the first state, the second phase locked loop compares a signal representative of the bus voltage to a second reference signal derived from an output voltage of the second inverter to drive the output voltage of the second inverter into substantial phase with the bus voltage, and, when the second controlled switch is in the second state, the second phase locked loop compares a signal derived from an output current of the second inverter to the second reference signal derived from the output voltage of the second inverter to reduce a cross conduction current flowing between the first and second inverters.

20. A method of reducing cross conduction current flowing between at least two parallel inverters in a redundant power supply comprising the steps of:

providing a reference signal which is approximately 90 degrees out of phase with an output voltage of a first one of the inverters;

providing an input signal representative of an output current of the first inverter;

multiplying the input signal and the reference signal to develop a difference signal;

filtering and sampling the difference signal; and

adjusting the phase of the output voltage of the first inverter and the reference signal to reduce the difference signal whereby cross conduction current flowing between the at least two parallel inverters is reduced.

21. A method as defined in claim 20 further comprising the step of integrating the difference signal over a predetermined time period.

22. A method as defined in claim 21 wherein the step of filtering and sampling the difference signal is performed by periodically filtering and sampling the integrated difference signal.

26. A method as defined in claim 20 wherein the cross conduction current flowing between the at least two parallel inverters is reduced without employing common control circuitry between the at least two parallel inverters.

29. A method as defined in claim 20 further comprising the steps of:

providing a second reference signal which is approximately 90 degrees out of phase with an output voltage of a second one of the inverters;

providing a second input signal representative of an output current of the second inverter;

multiplying the second input signal and the second reference signal to develop a second difference signal;

filtering and sampling the second difference signal; and

adjusting the phase of the output voltage of the second inverter and the second reference signal to reduce the difference signal whereby cross conduction current flowing between the at least two parallel inverters is reduced.