Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same

• US 6,118,696 A
• Filed: 05/04/1999
• Issued: 09/12/2000
• Est. Priority Date: 09/21/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T
• Application Number:
  US09/305,239
• Time in Patent Office: 497 Days
• Field of Search: 365/185.11, 365/185.13, 365/185.17, 365/185.01, 365/185.05, 365/185.07
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell array of a non-volatile semiconductor memory device includes unit strings grouped into first strings belonging to a first string group and second strings belonging to a second string group. Each unit string has a memory cells for storing data in a non-volatile state. Each first string is coupled between an associated bit line of a first bit line group and a first common source line whereas each second string is coupled between an associated bit line of a second bit line group and a second common source line. The bit lines and the common source lines are made of different conductive layers. In accordance with the invention, it is possible to achieve a less critical layout of sense amplifiers coupled to bit lines while easily performing a photolithography process as required in the manufacture of the memory device.

Claims

1. A non-volatile semiconductor memory cell array comprising:

a first group of units strings;

a second group of unit strings, wherein the second group of units is arranged substantially in parallel with the first group of units strings such that strings from the first group alternate with strings from the second group;

a second common source line arranged substantially orthogonal to the unit strings and coupled to each unit string of the second group of unit strings;

a first group of bit lines arranged substantially in parallel with the unit strings, wherein each bit line of the first group of bit lines is coupled to a corresponding unit string of the first group of unit strings;

a second group of bit lines arranged substantially in parallel with the unit strings, wherein each bit line of the second group of bit lines is coupled to a corresponding unit string of the second group of unit strings;

wherein the bit lines are formed on a different level than the common source lines.

2. A memory cell array according to claim 1 wherein:

each unit string has a first end at a first side of the memory cell array and a second end at a second side of the memory cell array opposite the first side;

the first and second common source lines are arranged along the first and second sides of the memory cell array, respectively;

the first end of each unit string of the first group of unit strings is coupled to the first common source line; and

the second end of each unit string of the second group of unit strings is coupled to the second common source line.

3. A memory cell array according to claim 2 wherein:

each bit line of the first group of bit lines is coupled to the second end of a corresponding unit string of the first group of unit strings; and

each bit line of the second group of bit lines is coupled to the first end of a corresponding unit string of the second group of unit strings.