Source bias compensation for page mode read operation in a flash memory device

• US 6,118,702 A
• Filed: 10/19/1999
• Issued: 09/12/2000
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Shieh, Ming-Huei, Venkatesh, Bhimachar
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/421,151
• Time in Patent Office: 329 Days
• Field of Search: 365/185.21, 365/185.22, 365/185.2, 365/185.11, 365/185.12, 365/210, 365/238.5
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A page mode memory senses a large number of bits simultaneously. The associated read current creates a source bias in the core cells which alters the sense margin at the sense amplifier. To address this problem, a memory integrated circuit (100) includes an array (102) of core cells, each core cell having a ground node (220, 222, 224). A ground line (230) couples the ground node of each core cell to a ground potential (Vss) and establishes a variable parasitic potential between the ground node and Vss. For sensing the data state of the core cells, a reference core cell (252) matches the array core cells and has a reference ground node (262). A circuit element (256) is coupled between the reference ground node and Vss to establish a variable reference potential to match the variable parasitic potential.

Claims

1. A memory comprising:

an array of core cells, each core cell including a ground node;

a ground line coupling the ground node of each core cell to a ground potential, the ground line establishing a variable parasitic potential between a ground potential and the ground node of each core cell;

a reference core cell including a reference ground node; and

a circuit element coupled between the reference ground node and the ground potential and configured to establish a variable reference potential to match the variable parasitic potential.

2. The memory of claim 1 wherein the ground line comprises a resistive portion of each core cell electrically coupled with resistive portions of adjacent core cells.

3. The memory of claim 1 further comprising:

a sensing circuit coupled to the array of core cells and the reference core cell and configured to compare a core cell current in a core cell and a reference current in the reference core cell.

4. The memory of claim 3 wherein the circuit element adjusts the reference current to match variation in the core cell current due to the variable parasitic potential.

5. The memory of claim 1 wherein the circuit element is configured to vary the variable reference potential in response to a number of core cells selected for sensing.

6. The memory of claim 5 wherein the circuit element establishes the variable reference potential in response to stored data states of the core cells selected for sensing.

7. The memory of claim 6 further comprising:

a sensing circuit configured to sense the stored data states of the core cells selected for sensing.

8. The memory of claim 7 wherein the circuit element establishes the variable reference potential in response to position in the core cell array of the core cells selected for sensing.

9. The memory of claim 7 further comprising:

a control circuit coupled to the circuit element to control the circuit element in establishing the variable reference potential.

10. A method of sensing states of a plurality of core cells in a memory integrated circuit, the method comprising the steps of:

selecting a word line of a plurality of word lines;

sensing a bit line current in a selected core cell;

sensing a reference current in a reference core cell; and

applying a bias potential to the reference core cell to match parasitic bias in the selected core cell.

11. The method of claim 10 further comprising the step of:

determining the parasitic bias at the selected core cell.

12. The method of claim 11 wherein the step of determining the parasitic bias comprises the step of:

determining the parasitic bias in response to a number of core cells selected.

13. The method of claim 12 wherein the step of determining the parasitic bias comprises the step of:

determining the parasitic bias in response to stored data states of selected core cells.

14. The method of claim 13 wherein the step of determining the parasitic bias comprises the step of:

determining the parasitic bias in response to position of the selected core cell in a core cell array of the memory.

15. A page mode memory in which a plurality of multi-bit words are sensed substantially and presented for reading one word at a time, the page mode memory comprising:

a core cell array including a plurality of core cells, each core cell when selected conducting one of a first current and a second current depending on stored data state of the core cell, each core cell including a parasitic element introducing a variable parasitic potential between the core cell and ground potential;

a sensing circuit configured to sense stored data states of a plurality of core cells;

a reference core cell configured to conduct a reference current for comparison by the sensing circuit with core cell current from selected core cells; and

a circuit element coupled with the reference core cell and configured to introduce a variable reference potential in response to the variable parasitic potential.

16. The page mode memory of claim 15 wherein the circuit element varies the variable reference potential to match variation of the variable parasitic potential.