Method and apparatus for a flexible access rate common-memory packet switch
First Claim
1. A method of controlling port access to the common-memory of a common-memory multi-port data packet switch, comprising:
- defining a control cycle consisting of a fixed number of discrete common-memory access time slots;
allocating a proportional number of the access time slots to each port based on a predetermined access capacity requirement for the port; and
distributing access time slots for each port in the control cycle in such a way as to reduce packet transfer delay and jitter.
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Accused Products
Abstract
A method of controlling asymmetrical port access in a common-memory (CM) multi-port data packet switch and a high-capacity flexible access rate CM data packet switch are described. The method involves providing a common-memory-access control table which defines a unique contiguous band of CM access time slots allocated to each port of the packet switch. Each access time slot is identified by a time slot identifier. Time slot identifiers are generated at a regular interval. The time slot identifiers are generated so that CM access time for each port is substantially equally spaced to minimize delay jitter. The packet switch may have an equal number of input and output ports, or more output ports than input ports. In the high-capacity CM packet switch, several CM switch modules are interlinked by middle buffers in a folded configuration to provide a packet switch having Terabit output capacity. The advantage is a packet switch architecture which supports flexible access rates to eliminate idle switch capacity, the CM access time slots being substantially equally spaced apart to reduce packet transfer delay jitter.
36 Citations
16 Claims
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1. A method of controlling port access to the common-memory of a common-memory multi-port data packet switch, comprising:
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defining a control cycle consisting of a fixed number of discrete common-memory access time slots; allocating a proportional number of the access time slots to each port based on a predetermined access capacity requirement for the port; and distributing access time slots for each port in the control cycle in such a way as to reduce packet transfer delay and jitter.
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2. A method of controlling asymmetrical port access in a common-memory multi-port data packet switch, comprising:
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a) at least during each execution of an initialization process for the data packet switch, inspecting a common-memory-access control table to determine a lower bound and an upper bound of a unique contiguous band of common-memory access time slots allocated to each port and passing the lower bound and the upper bound to a controller for each port; b) continuously maintaining a cyclic count having a maximum value equal to the number of access time slots allocated in the control table; and c) applying a scatter transform to the count each time it is incremented to obtain a scattered transform result, whereby each port controller is enabled to access the common-memory when the transform result is greater than or equal to the lower bound and less than the upper bound passed to the port controller. - View Dependent Claims (3, 4, 5, 6)
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7. A flexible access rate common-memory packet switch, comprising:
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a plurality of input ports and output ports; a common-memory for switching packets between the input ports and the output ports; means for storing an allocation of common-memory access time slots for each port, the allocation being based on a predetermined access capacity requirement for the port; and means for distributing the access time slots for each port in a control cycle of all access time slots allocated in such a way that each port accesses the common-memory in a cyclic sequence of substantially equally spaced access time slot intervals.
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8. A flexible access rate common-memory packet switch, comprising:
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a common-memory switch module having an ingress side and an egress side; a plurality of input ports connected to the ingress side of the common-memory switch module; a plurality of output ports connected to the egress side of the common-memory switch module; a smoothing buffer associated with each of the input and output ports; a common-memory-access control table for defining a unique contiguous band of discrete access time slot allocations for access to the common-memory by each of the input and output ports; means for sequentially generating time slot identifiers so that access to the common-memory switch module is enabled for each port in a substantially evenly spaced relationship; and means for enabling a specific port to access the common-memory switch module when a time slot identifier indicates a time slot within the contiguous band allocated to that port. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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Specification