GPS receiver with efficient signal acquisition

• US 6,118,808 A
• Filed: 06/26/1997
• Issued: 09/12/2000
• Est. Priority Date: 07/12/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Harrison, Daniel David, Tiemann, Jerome Johnson
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): PARK, ALBERT C
• Application Number:
  US08/883,159
• Time in Patent Office: 1,174 Days
• Field of Search: 375/200, 375/202, 375/206, 375/208, 375/209, 375/210, 455/343, 455/524, 455/384, 342/352, 342/357
• US Class Current: 375/142
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/42 Determining position
• CPC Class Codes: G01S 5/0027 of actual mobile position, i.e. position determined on mobile
• CPC Class Codes: G01S 5/0036 of measured values, i.e. measurement on mobile and position calculation on base station
• CPC Class Codes: G01S 5/0054 of actual mobile position, i.e. position calculation on base station
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 2201/70709 with discontinuous detection
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A direct sequence spread spectrum receiver samples an incoming signal and translates the signal to an IF signal. The IF signal is sampled and stored in memory. In one embodiment, the memory consists of two memory banks which alternately receive sample segments. During a write period to one of the memory banks, the other memory bank supplies its output to a processor. This continues in a ping-pong manner. In another embodiment, a single memory bank is filled and read as necessary, the receiver ignoring incoming signal until the processor has completed processing the sample available at the output of the memory. Such a receiver is useful in global positioning satellite (GPS) signal processing where the incoming signal contains several satellite transmissions encoded with CDMA encoding.

Claims

1. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, apparatus comprising:

a tuner for receiving at least one of said signals and producing an intermediate frequency signal, said tuner including a converter for sampling said intermediate frequency signal;

a first and a second memory for alternately storing sampled segments of said intermediate frequency signal;

a processor for alternately reading and processing said segments;

a controller for controlling the alternate storage and the alternate processing of said segments.

2. The receiver of claim 1, wherein:

said receiver comprises a GPS receiver and said transmitters comprise GPS transmitters carried by satellites.

3. The receiver of claim 1, wherein:

said processor comprises a correlator.

7. The receiver of claim 1, wherein:

said processor is adapted to produce a coherent result capable of being combined with other coherent results from said processor, wherein the combined coherent results exceed a threshold for indicating identification of said signal.

8. The receiver of claim 1, wherein:

said segments are representative of one millisecond of said intermediate frequency signal.

9. The receiver of claim 1, wherein:

said processor is adapted to read a stored segment of said intermediate frequency signal from said first memory while said second memory stores another segment of said intermediate frequency signal from said tuner.

10. The receiver of claim 1, wherein:

said processor is adapted to process sequential segments of said intermediate frequency signal until a data set is processed.

11. The receiver of claim 1, wherein:

each of said first and second memories is adapted to provide digital data samples of intermediate frequency signal segments stored therein, in parallel.

12. The receiver of claim 11, wherein:

lengths of said first memory, said second memory, and said processor are equal.

13. The receiver of claim 1, further comprising:

a third memory, a fourth memory, and a second processor, wherein;

said third memory, said fourth memory and said second processor substantially duplicate said first memory, said second memory and said processor, such that said first memory, said second memory and said processor are adapted to receive in-phase intermediate frequency signal segments, and said third memory, said fourth memory and said second processor are adapted to receive quadrature phase intermediate frequency signal segments.

14. The receiver of claim 1, further comprising:

a front-end memory for storing said intermediate frequency signal segments from said tuner, said signal segments comprising a data set, and for supplying said first memory and said second memory with time segments from the stored signal segments, wherein power to said tuner is inhibited after said data set is sampled and stored in said front-end memory.

15. The receiver of claim 1, further comprising:

a replica signal generator for providing to said processor a replica signal having a replica code and a code offset.

16. The receiver of claim 15, wherein:

said processor is adapted to compare said replica signal to said intermediate frequency signal segments to produce a coherent result.

4. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, a method comprising the steps of:

receiving a first time segment of at least one of said signals;

converting said time segment of said signal to a multiple-sample digital form;

storing said multiple-sample digital form in a memory, said memory having an output signal comprising said multiple-sample digital form;

applying said multiple-sample digital form simultaneously from said memory into a processor; and

processing said multiple-sample digital form;

wherein

time segments of said signals arriving at said receiver subsequent to said first time segment are skipped during said processing step.

5. The method of claim 4, wherein:

said receiver comprises a GPS receiver and said transmitters comprise GPS transmitters carried by satellites.

6. The method of claim 4, wherein:

said processing comprises the step of correlating the first time segment with local pseudo random noise code sequences.

17. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, apparatus comprising:

a tuner for receiving at least one of said signals and producing an intermediate frequency signal, said tuner including a converter for sampling said intermediate frequency signal to provide segments thereof;

a memory for storing every other segment of said intermediate frequency signal;

a processor for reading and processing the intermediate frequency signal segments; and

a controller for controlling the storage and the processing of said intermediate frequency signal segments.

18. The receiver of claim 17, wherein

said receiver comprises a GPS receiver, and said transmitters comprise GPS transmitters carried by satellites.

19. The receiver of claim 17, wherein:

said processor comprises a parallel correlator.

20. The receiver of claim 17, wherein:

said processor is adapted to produce a coherent result capable of being combined with other coherent results from said processor, wherein the combined coherent results exceed a threshold for indicating identification of said one of said signals.

21. The receiver of claim 17, wherein:

each of said segments is representative of a respective one millisecond portion of said intermediate frequency signal.

22. The receiver of claim 17, wherein:

said processor is adapted to process sequential segments until a data sequence is processed.

23. The receiver of claim 17, wherein:

said processor is adapted to read in parallel said segments in said memory.

24. The receiver of claim 17, further comprising:

a front-end memory for receiving a data segment from said tuner, and for supplying said memory with a portion of said data segment, wherein power to said tuner is inhibited after said data segment is stored in said front-end memory.

25. The receiver of claim 17, further comprising:

a replica signal generator for providing to said processor a replica signal having a replica code and an offset code.

26. The receiver of claim 25, wherein:

said processor is adapted to compare said replica signal to said intermediate signal segments to produce a coherent result.

27. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, a method comprising the steps of:

(a) receiving a segment of a signal;

(b) converting the received segment of said signal to one multiple-sample digital segment;

(c) storing said one multiple-sample digital segment in a memory;

(d) transferring said one multiple-sample digital segment from said memory to a processor;

(e) storing a second multiple-sample digital segment in said memory, wherein said one and said second multiple-sample digital segments are alternately stored in said memory and transferred from said memory for processing;

(f) processing alternately the transferred one multiple-sample digital segment and the transferred second multiple-sample digital segment; and

(g) repeating steps (a) to (f) until a data segment sufficient for signal acquisition is processed.

28. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, a method comprising the steps of:

(a) receiving at least one of said signals;

(b) converting said signal to a multiple-sample digital signal, said multiple-sample digital signal comprising a data segment;

(c) storing said multiple-sample digital signal in a front-end memory;

(d) inhibiting power to said tuner;

(e) transferring a portion of said multiple-sample digital signal to a segment memory having a parallel sample output;

(f) supplying said portion from said parallel sample output to a parallel processor;

(g) processing said portion by calculating the inner product of said portion and a C/A replica code sequence; and

(h) repeating steps (e) and (g) until said data segment is processed.