Digital super-regenerative detector RF receiver

• US 6,118,828 A
• Filed: 08/08/1997
• Issued: 09/12/2000
• Est. Priority Date: 06/05/1995
• Status: Expired due to Fees

• Current Assignee: The Chamberlain Group, Inc. (The Chamberlain Group LLC)
• Original Assignee: The Chamberlain Group, Inc. (The Chamberlain Group LLC)
• Inventors: Schleifer, Fred Freybler
• Primary Examiner(s): Vo, Don N.
• Application Number:
  US08/907,469
• Time in Patent Office: 1,131 Days
• Field of Search: 375/219, 375/316, 375/317, 375/318, 340/825.57, 340/825.53, 340/825.61, 340/825.69, 341/176
• US Class Current: 375/317
• CPC Class Codes: H03D 11/00 Super-regenerative demodulator circuits applications in responders G01S
• CPC Class Codes: H03D 11/08 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A digital super-regenerative receiver has an analog RF detector and a regenerative oscillator. An output signal of the analog RF detector is used to generate a digital signal from which an oscillator bias is adjusted in order to maintain the oscillator start-up time at a fixed level. The circuit senses through the use of a multi-level threshold detector if the start-up time is earlier or later than the predetermined start-up time and produces an output signal when the majority of the start times are ahead of the expected start time.

Claims

1. A super-regenerative digital radio frequency receiver for receiving a radio frequency signal comprising:

a regenerative radio frequency oscillator for receiving radio frequency signals and for oscillating in response thereto and producing an oscillator signal;

an enable circuit coupled to said radio frequency oscillator for enabling oscillations of the radio frequency oscillator from time to time;

a multi-level threshold detecting circuit coupled to receive an output of the radio frequency oscillator, the threshold detecting circuit receiving the radio frequency signal and determining when the radio frequency signal from the radio frequency oscillator due to increasing oscillation therein exceeds a threshold, the threshold detecting circuit providing a threshold output signal as a result thereof, the multi-level threshold detector circuit being coupled to the enable circuit to disable the radio frequency oscillator; and

a digital detector connected to the output of the threshold detector for providing a bit signal therefrom in response to the digital detector receiving at least n of m recent threshold output signals.

2. A super-regenerative receiver according to claim 1 further comprising a framing circuit for combining bits in response to the bit signal received from the digital detector circuit into data frames.

3. A super-regenerative radio frequency receiver according to claim 2 wherein the threshold for the threshold detector may be dynamically set in response to outputs from the threshold detector.

4. A super-regenerative receiver according to claim 1 wherein the output bit signal controls the response of a motor control circuit connected thereto, said motor control circuit being adapted to provide output current to an electric motor.

5. A receiver for receiving a digitally coded radio frequency signal from a transmitter, comprising:

an RF detector for detecting the digitally coded radio frequency signal and for generating a digital signal responsive to the digitally coded radio frequency signal, the RF detector comprising an analog amplifier coupled to an analog oscillator for generating an analog oscillator signal and a digital signal generator responsive to the analog oscillator signal for producing a digital signal;

a clock signal generator for producing a clock signal;

a delayed clock signal generator for generating a first plurality of offset clock signals and a second offset clock signal in response to the clock signal; and

a first comparator for comparing the combined one of the first plurality of clock offset signals and the second offset clock signal with the digital signal and producing a combination clocked and analog bias signal and supplying the combination clocked and analog bias signal to the oscillator to stabilize the oscillator timing; and

a second comparator for comparing the first offset signal with the digital signal and generating a detected code signal in response thereto.

6. A receiver according to claim 5, further comprising a majority pulse detector coupled to receive the detected code signal and for producing an accepted code signal in response to receipt of a predetermined number of code signals.