Apparatus and method for automatic mode selection in a communications receiver

• US 6,118,829 A
• Filed: 10/01/1997
• Issued: 09/12/2000
• Est. Priority Date: 10/01/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Integration Associates, Inc. (Silicon Laboratories Incorporated)
• Inventors: North, Brian B.
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US08/942,312
• Time in Patent Office: 1,077 Days
• Field of Search: 375/344, 375/345, 375/316, 375/287, 375/377, 375/318, 375/319, 375/317, 455/138, 455/140, 455/184.1, 455/177.1, 455/197.2, 455/199.1, 455/219, 455/232, 455/234.1, 330/254, 330/260, 330/278, 327/1, 327/10, 327/16, 327/555
• US Class Current: 375/317
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only

Abstract

A method and apparatus are shown for automatically adjusting a response bandwidth and input sensitivity of a communications receiver responsive to a frequency of a received data signal. The response bandwidth is adjusted by switching a low pass filter into a receive path of the receiver when the received data signal is a low speed data signal and switching the low pass filter out of the receive path when the received data signal is a high speed data signal. The input sensitivity is adjusted by either changing a detection threshold of a comparator in the receive path or varying a gain of an input amplifier in the receive path. The high speed data signal is discerned when the low pass filter limits the response bandwidth of the receiver by a mode selection circuit which examines the duration of multiple pulses in a pulse train in the received data signal.

Claims

1. A receiver circuit, the circuit comprising:

a circuit input terminal configured to receive an input data signal;

a circuit output terminal;

an input amplifier having input and output terminals, the input terminal of the input amplifier being coupled to the circuit input terminal;

a first comparator having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the input amplifier, the second input terminal being configured to receive a detection threshold voltage, and the output terminal of the first comparator being coupled to the circuit output terminal;

a filter;

a switch coupled in series with the filter between the first input terminal of the first comparator and a first power supply rail, the switch having a control terminal, wherein the switch is configured to switch to a first position responsive to receiving a low speed mode control signal at the control terminal of the switch, and further wherein the switch is configured to switch to a second position responsive to receiving a high speed mode control signal at the control terminal of the switch, and further wherein the switch is configured to switch to a second position responsive to receiving a high speed mode control signal at the control terminal of the switch; and

a mode selection circuit having input and output terminals, wherein the input terminal of the mode selection circuit is coupled to the output terminal of the first comparator and the output terminal of the mode selection circuit is coupled to the control terminal of the switch, and further wherein the mode selection circuit is configured to generate the low speed mode control signal responsive to a low speed data signal generated at the output of the first comparator responsive to the input data signal and generate the high speed mode control signal responsive to a low speed data signal generated at the output of the first comparator responsive to the input data signal.

2. The receiver circuit of claim 1, further including a variable voltage generator having an output terminal coupled to the second input terminal of the first comparator and a control terminal coupled to the output terminal of the mode selection circuit, wherein the variable voltage generator is configured to generate the detection threshold voltage at the output terminal of the variable voltage generator, the variable voltage generator being configured to set the detection threshold voltage to a first detection threshold voltage level responsive to the low speed mode control signal and set the detection threshold voltage to a second detection threshold voltage level responsive to the high speed mode control signal.

3. The receiver circuit of claim 1, wherein the input amplifier further includes a control terminal, wherein the control terminal of the input amplifier is coupled to the output terminal of the mode selection circuit, the input amplifier being configured to amplify with a first gain level responsive to the low speed mode control signal and a second gain level responsive to the high speed mode control signal, wherein the first gain level is greater than the second gain level.

4. The receiver circuit of claim 1, wherein the filter further comprises:

a resistor coupled between the output terminal of the input amplifier and a second power supply rail; and

a capacitor coupled in series with the switch between the output terminal of the input amplifier and the first power supply rail.

5. The receiver circuit of claim 1 wherein the mode selection circuit is further configured to time a period between transitions in a data signal generated at the output of the first comparator and output the low speed mode control signal when the period between transitions is greater than a first predetermined time value and output the high speed mode control signal when the period between transitions is between a second predetermined time value and the first predetermined time value, where the first predetermined time value is greater in magnitude than the second predetermined time value.

6. The receiver circuit of claim 5 wherein the mode selection circuit is still further configured to initially output the low speed mode control signal and output a current mode control signal when the time between transitions is less than the second predetermined time value, wherein the current mode control signal is one of the high and low speed mode control signals.

7. The receiver circuit of claim 1 wherein the mode selection circuit is further configured to initially generate the low speed mode control signal and to time the duration of a first pulse and the duration of a second pulse in a data signal generated at the output of the first comparator and output the low speed mode control signal when the duration of each of the first and second pulses is greater than a predetermined low speed threshold value, wherein the first and second pulses are sequential to one another.

8. The receiver circuit of claim 7 wherein the mode selection circuit is still further configured to measure the duration of a third pulse in the data signal generated at the output of the first comparator and output the high speed mode control signal when the duration of each of the first and third pulses is less than the the predetermined low speed threshold value.

9. The receiver circuit of claim 1, wherein the mode selection circuit further includes:

a timer configured to receive the data signal generated at the output of the comparator and generate a timing signal responsive to each pulse in the data signal that corresponds to the duration of each pulse;

a second comparator having first and second input terminals and an output terminal, wherein the first input terminal of the second comparator is configured to receive the timing signal generated by the timer and the second input terminal is configured to receive a first reference value, the comparator being configured to output a timer signal having a first timer value corresponding to a low speed pulse and a second timer value corresponding to a high speed pulse;

a storage register configured to store the timer signal responsive to each pulse in the data signal;

a combinational circuit configured to receive the timer signal stored in the storage register and, responsive thereto, output the low speed mode control signal responsive to the first timer value and output the high speed mode control signal responsive to the second timer value.

10. The receiver circuit of claim 9, wherein:

the storage register is further configured to store the timer signal for three sequential pulses in the data signal; and

the combinational circuit is further configured to output the low speed mode control signal when the timer signal stored for a first one of the three sequential pulses is the first timer value and the timer signal stored for a second one of the three sequential pulses is the second timer value, and further wherein the combinational circuit is configured to output the high speed mode control signal when the timer signal stored for the first one of the three sequential pulses is the second timer value and the timer signal stored for a third one of the three sequential pulses is the second timer value.

11. A receiver circuit, the circuit comprising:

a circuit input terminal configured to receive an input data signal;

a circuit output terminal;

an input amplifier having input and output terminals, the input terminal of the input amplifier being coupled to the circuit input terminal;

a first comparator having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the input amplifier, the second input terminal being configured to receive a detection threshold voltage, and the output terminal of the first comparator being coupled to the circuit output terminal;

a filter;

a switch coupled in series with the filter between the output terminal of the input amplifier and a first power supply rail, the switch having a control terminal, wherein the switch is configured to switch to a first position responsive to receiving a low speed mode control signal at the control terminal of the switch, and further wherein the switch is configured to switch to a second position responsive to receiving a high speed mode control signal at the control terminal of the switch, and further wherein the switch is configured to switch to a second position responsive to receiving a high speed mode control signal at the control terminal of the switch; and

a mode selection circuit having input and output terminals, wherein the input terminal of the mode selection circuit is coupled to the output terminal of the first comparator and the output terminal of the mode selection circuit is coupled to the control terminal of the switch, and further wherein the mode selection circuit is configured to generate the low speed mode control signal responsive to a low speed data signal generated at the output of the first comparator responsive to the input data signal and generate the high speed mode control signal responsive to a high speed data signal generated at the output of the first comparator responsive to the input data signal, and where the mode selection circuit further includes;

a timer configured to receive the data signal generated at the output of the comparator and generate a timing signal responsive to each pulse in the data signal that corresponds to the duration of each pulse,

a second comparator having first and second input terminals and an output terminal, wherein the first input terminal of the second comparator is configured to receive the timing signal generated by the timer and the second input terminal is configured to receive a first reference value, the comparator being configured to output a timer signal having a first timer value corresponding to a low speed pulse and a second timer value corresponding to a high speed pulse,

a storage register configured to store the timer signal responsive to each pulse in the data signal, where the storage register is further configured to store the timer signal for three sequential pulses in the data signal, and

a combinational circuit configured to receive the timer signal stored in the storage register and, responsive thereto, output the low speed mode control signal responsive to the first timer value and output the high speed mode control signal responsive to the second timer value, where the combinational circuit is further configured to output the low speed mode control signal when the timer signal stored for a first one of the three sequential pulses is the first timer value and the timer signal stored for a second one of the three sequential pulses is the second timer value, and further wherein the combinational circuit is configured to output the high speed mode control signal when the timer signal stored for the first one of the three sequential pulses is the second timer value and the timer signal stored for a third one of the three sequential pulses is the second timer value;

a third comparator having first and second input terminals and an output terminal, wherein the first input terminal of the third comparator is configured to receive the timing signal generated by the timer and the second input terminal is configured to receive a second reference value, the comparator being configured to output a hold signal, wherein the second reference value is smaller in magnitude than the first reference value;

a latch interposed between the circuit input terminal and the circuit output terminal wherein an output value of the latch is set when the data signal is a logical high value and the hold signal is a logical low value and wherein the output value of the latch is reset when the data signal is a logical low value; and

the timer is further configured to decrease the timing value at a predetermined rate responsive to a falling edge of each pulse in the data signal.

12. The receiver circuit of claim 11, wherein the predetermined rate corresponds to the duration of each pulse.

13. The receiver circuit of claim 11, wherein:

the third comparator is further configured to have hysteresis wherein the hold signal transitions from the logical low value to the logical high value responsive to the timing value being equivalent to a third reference value, wherein the third reference value is intermediate the first and second reference values, and the hold signal transitions from the logical high value to the logical low value responsive to the timing value being equivalent to the second reference value; and

the latch interposed between the circuit input and circuit output terminals is further configured to be reset when the hold signal is the logical high value and the data signal is the logical low value.

14. The receiver circuit of claim 13, wherein the timer further comprises:

a capacitor, wherein the timing signal is the voltage across the capacitor;

a current source configured to charge the capacitor at a first fixed rate; and

a current sink configured to discharge the capacitor at a second fixed rate responsive to the output value of the latch interposed between the circuit input and circuit output terminals, wherein the first fixed rate is less than the second fixed rate.

15. A method for receiving high and low speed signals in a receiver, the method comprising the steps:

providing a receive path configured to receive an input data signal, wherein the input data signal includes one of the high speed signal and the low speed signal;

comparing the input data signal to a detection threshold voltage in order to produce a demodulated data signal;

setting a receive response bandwidth of the receive path to a first bandwidth level responsive to a low speed mode control signal and to a second bandwidth level responsive to a high speed mode control signal, wherein the second bandwidth level is greater than the first bandwidth level;

generating the low speed mode control signal responsive to the low speed signal; and

generating the high speed mode control signal responsive to the high speed signal.

16. The method of claim 15, further including the steps:

generating the low speed mode control signal responsive to the absence of the high speed signal and the low speed signal; and

initially generating the low speed mode control signal in the presence of one of the high speed signal and the low speed signal.

17. The method of claim 15, wherein the step of setting the receive response bandwidth of the receive path includes the steps:

closing a capacitive path to a ground potential responsive to the low speed mode control signal; and

opening the capacitive path to the ground potential responsive to the high speed mode control signal.

18. The method of claim 15, wherein the step of generating the low speed mode control signal responsive to the low speed signal includes generating the low speed mode control signal when both a first and second pulse in the demodulated data signal are low speed pulses, wherein the second pulse is subsequent to the first pulse.

19. The method of claim 18, wherein the step of generating the low speed mode control signal when both a first and second pulse in the demodulated data signal are low speed pulses includes:

timing a duration of the first pulse;

timing a duration of the second pulse; and

generating the low speed mode control signal when the duration of the first pulse and the duration of the second pulse are each greater than a first predetermined value.

20. The method of claim 18, wherein the step of generating the high speed mode control signal responsive to the high speed signal includes generating the low speed mode control signal when both a first and third pulse in the demodulated data signal are high speed pulses, wherein the third pulse is subsequent to the second pulse.

21. The method of claim 20, wherein the step of generating the high speed mode control signal when both the first and a third pulse in the demodulated data signal are high speed pulses includes:

timing a duration of the first pulse;

timing a duration of the third pulse; and

generating the high speed mode control signal when both the duration of the first pulse and the duration of the second pulse are less than a first predetermined value.

22. The method of claim 21, wherein the steps of timing a duration of the first pulse, timing a duration of the second pulse and timing a duration of the third pulse are each accomplished by charging a capacitor at a first fixed rate responsive to a pulse in the input data signal.

23. The method of claim 22, further including the step of suppressing subsequent pulses in the demodulated data signal responsive to a preceding pulse in the demodulated data signal for a time interval that is proportional to a duration of the preceding pulse in the demodulated data signal.

24. The method of claim 23, wherein the step of suppressing subsequent pulses in the demodulated data signal responsive to a preceding pulse in the demodulated data signal includes:

generating a hold signal by discharging the capacitor at a second fixed rate responsive to a falling edge of the preceding pulse, wherein the second fixed rate is greater than the first fixed rate; and

gating the demodulated data signal with the hold signal in order to produce an output data signal.

25. The method of claim 24, further including the step of delaying a falling edge of a pulse in the output data signal responsive to a rising edge of a corresponding pulse in the demodulated data signal when the duration of the corresponding pulse in the demodulated data signal is less than a minimum pulse width threshold.

26. The method of claim 25, wherein the step of delaying a falling edge of a pulse in the output data signal further includes the steps:

buffering the demodulated signal with a latch in order to produce the output data signal; and

preventing the latch from being reset responsive to the hold signal.

27. The method of claim 15, wherein the step of comparing the input data signal to a detection threshold voltage in order to produce a demodulated data signal further includes the steps:

setting the detection threshold voltage to a first voltage level responsive to a low speed mode control signal; and

setting the detection threshold voltage to a second voltage level responsive to a high speed mode control signal, wherein the second voltage level is greater than the first voltage level.

28. The method of claim 15, further including the step of amplifying the input data signal, wherein the input data signal is amplified with a first gain factor responsive to the low speed mode control signal, and the the input data signal is amplified with a second gain factor responsive to the high speed mode control signal, wherein the first gain factor is greater than the second gain factor.

29. A communications receiver, the receiver comprising:

amplifier means for receiving an input data signal and amplifying the input data signal to produce an amplified data signal;

demodulating means for transforming the amplified data signal into a demodulated data signal;

filtering means for filtering the amplified data signal;

switching means coupled in series with the filtering means for activating the filtering means responsive to a low speed mode signal and deactivating the filtering means responsive to a high speed mode signal; and

mode selection means for monitoring the demodulated data signal and, responsive to a low speed pulse train in the demodulated data signal, generating the low speed mode signal and, responsive to a high speed pulse train in the demodulated data signal, generating the high speed mode signal.

30. The communications receiver of claim 29, wherein the demodulating means is further configured to compare the amplified data signal to a first detection threshold to produce the demodulated data signal responsive to the low speed mode signal and compare the amplified data signal to a second detection threshold to produce the demodulated data signal responsive to the high speed mode signal.

31. The communications receiver of claim 29, wherein the amplifier means is further configured to amplify the input data signal by a first gain factor responsive to the low speed mode signal and amplify the input data signal by a second gain factor responsive to the high speed mode signal.

32. The communications receiver of claim 29, wherein the mode selection means further comprises:

timer means for timing a duration of a pulse in the demodulated data signal in order to produce a timing signal;

comparison means for comparing the timing signal to a first reference value in order to produce a timer signal having a high speed state when the timing signal is less than the first reference value and a low speed state when the timing signal is greater than or equal to the first reference value;

storage means for storing the timer signal responsive to each pulse in the demodulated data signal; and

combinational logic for generating the low speed mode signal responsive to the low speed state of the timing signal being stored in the storage means and generating the high speed mode signal responsive to the high speed state of the timing signal being stored in the storage means.

33. The communications receiver of claim 32, wherein:

the storage means is further configured to store the timing signals corresponding to multiple sequential pulses in the demodulated data signal; and

the combinational logic is further configured to generate the low speed mode signal responsive to a low speed state being stored for each of first and second pulses of the multiple sequential pulses and generating the high speed mode signal responsive to a high speed state being stored for each of the first pulse and a third pulse of the multiple sequential pulses.

34. The communications receiver of claim 32, wherein the mode selection means further comprises:

buffering means for buffering the demodulated data signal in order to produce an output data signal;

hold-off means for comparing the timing signal to a second reference value in order to prevent the buffering means from transitioning responsive to the demodulated data signal while the timing signal is greater than the second reference value, wherein the first reference value is greater than the second reference value; and

wherein the timing means is further configured to decrease the timing signal at a predetermined rate responsive to a falling edge in the output data signal.

35. The communications receiver of claim 34, wherein the hold-off means is further configured to prevent the buffering means from resetting the output data signal until the timing signal exceeds a third reference value, wherein the third reference value is greater than the second reference value and less than the first reference value.