Digital DC restoration device

• US 6,118,830 A
• Filed: 04/14/1998
• Issued: 09/12/2000
• Est. Priority Date: 04/15/1997
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Vorenkamp, Pieter, Thies, William
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): McKiernan, Thomas E
• Application Number:
  US09/060,088
• Time in Patent Office: 882 Days
• Field of Search: 375/319, 375/317, 375/287, 375/345, 359/195
• US Class Current: 375/319
• CPC Class Codes: H03M 1/1295 Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
• CPC Class Codes: H04N 5/18 by means of "clamp" circuit operated by switching circuit

Abstract

This device includes a main signal path in which a capacitor is included upstream of an analog/digital converter in which a conversion is triggered by a clock. According to the invention, the output of the analog/digital converter is connected to inputs of several threshold detectors which have positive detection thresholds in a progression proportional to consecutive powers of two, and several other threshold detectors which have negative detection thresholds which also progress proportionally to consecutive powers of two, which threshold detectors control current generators whose currents are added together into the capacitor.

Claims

1. An integrated circuit comprising inter alia a DC restoration device which has a main signal path in which a capacitor is included upstream of an analog/digital converter in which a conversion is triggered by a clock, comprising threshold detectors each provided with an input and an output and means for supplying at the output a logic signal if the input voltage exceeds a given threshold value which is different for each threshold detector, and comprising at least two current generators each provided with a control input and with a current output and with means for supplying upon command a calibrated current which is to be fed into the capacitor, the output of the analog/digital converter being connected jointly to the inputs of all threshold detectors, characterized in that several threshold detectors have a positive detection threshold such that the threshold voltage levels from one detector to the next show a progression proportional to successive powers of two, and several other threshold detectors have a negative detection threshold such that the absolute threshold voltage values also show a progression proportional to successive powers of two, while a current generator corresponds to each threshold detector, the outputs of all the current generators being connected such that their currents are added together.

2. An integrated circuit as claimed in claim 1, characterized in that the output of each threshold detector is connected to the signal input of a first flipflop D whose output is connected to a first input of a gate ET whose output is connected to the control input of one of the current generators, and the clock connection is connected to the input of a divider-by-two whose output is connected to the clock input of each of the first flipflops D as well as to a second input of each of the gates ET.

3. An integrated circuit as claimed in claim 2, characterized in that a switch controlled by a control signal is included between the current generators and the capacitor, and the control signal for the switch is also connected to the zero reset inputs of the first flipflops D.

4. An integrated circuit as claimed in claim 1, characterized in that the current generators corresponding to the consecutive detectors having the highest absolute threshold values supply progressive calibrated currents which are proportional to successive powers of two.

5. An integrated circuit as claimed in claim 1, characterized in that the device further comprises two supplementary gates of the ET type whose outputs are connected to respective control inputs of two supplementary current generators whose outputs are connected so as to add their currents to those of the other current generators, and two sign detectors each provided with an input and with an output and with means for delivering a logic signal at the output in dependence on the sign of the input voltage, the output of each of the sign detectors being connected to the input of one of the supplementary ET gates, while the inputs of the two sign detectors are jointly connected to the output of the analog/digital converter, and the calibrated current delivered by the supplementary current generators is at least several tens of times lower in value than that delivered by the other current generators.

6. An integrated circuit as claimed in claim 5, characterized in that the threshold values of the detectors having the lowest threshold are programmable.

7. An integrated circuit as claimed in claim 5, characterized in that the analog/digital converter is of a folding type.

8. An integrated circuit as claimed in claim 1, characterized in that the main path further comprises an amplifier with controllable gain placed between the capacitor and the analog/digital converter.

9. An integrated circuit as claimed in claim 8, characterized in that it comprises means for adjusting the calibrated current delivered by the current generators in dependence on the gain of the amplifier.