Speculative cache line write backs to avoid hotspots

• US 6,119,205 A
• Filed: 12/22/1997
• Issued: 09/12/2000
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Pong, Fong, Hetherington, Ricky C., Wicki, Thomas M., Kasinathan, Meera
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/995,779
• Time in Patent Office: 995 Days
• Field of Search: 711/136, 711/143, 711/137, 711/122, 711/129, 711/134, 711/135, 711/144
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence

Abstract

A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where each entry comprises tag information for accessing the data cache. The tag information includes state information indicating whether the represented cache line includes dirty data. A speculative write back unit monitors the state information and is operative to initiate a write back of a cache line having more than a preselected amount of dirty data.

Claims

1. A cache system comprising:

a data cache memory comprising a plurality of cache lines;

a tag store having an entry representing each line in the cache memory wherein each entry comprises tag information for accessing the data cache, the tag information including state information indicating whether the represented cache line includes dirty data; and

a speculative write back unit monitoring the state information and operative to initiate a write back of a cache line having more than a preselected amount of dirty data while maintaining the data in the cache line and updating the state information to indicate the represented cache line has non-dirty data.

2. The cache system of claim 1 further comprising a least recently used replacement mechanism initiating write back of selected cache lines wherein the selection is based upon time of last access.

3. The cache system of claim 1 wherein the speculative write back unit is operative to initiate a write back of a selected cache line without regard to frequency with which the selected cache line is accessed.

4. The cache system of claim 1 wherein the speculative write back unit is operative to initiate a write back of a selected cache line without regard to how recently the cache line was accessed.

5. The cache system of claim 1 wherein the data cache memory is sub-blocked and each cache line comprises a plurality of sub-blocks, each sub-block being represented by independent state data in the associated tag entry.

6. The cache system of claim 5 wherein the speculative write back unit monitors the state information for each of the sub-blocks in a cache line and is operative to initiate a speculative write back of a cache line when more than a preselected number of sub-blocks in a cache line include dirty data.

7. The cache system of claim 1 wherein the preselected amount of dirty data is selected to be a fixed percentage of dirty data in the cache line.

8. The cache system of claim 1 wherein the preselected amount of dirty data is dynamically set based upon the time of last accesses to each cache line.

9. The cache system of claim 1 wherein speculative write back unit is coupled to the tag store to receive the state information and address information held in the tag store each time a tag store entry is accessed.

10. The cache system of claim 1 wherein speculative write back unit is coupled to the tag store to initiate snoops of selected tag store entries to monitor the state information of the selected tag store entries.

11. The cache system of claim 1 wherein data cache memory is implemented on a separate integrated circuit from the tag store.

12. A computer system comprising:

a processor formed as an integrated circuit chip;

a cache system coupled to the processor, the cache system further comprising;

an on-chip cache comprising a plurality of cache lines;

a first on-chip tag store holding tag information for accessing the on-chip cache;

an off-chip sub-blocked data cache comprising a plurality of cache lines wherein each cache line in the off-chip data cache corresponds to a plurality of lines in the on-chip cache;

a second on-chip tag array holding tag information for accessing the off-chip data cache;

a replacement mechanism monitoring the tag information in the second on-chip tag array to initiate write back of selected LRU cache lines on a least recently used basis; and

a speculative write back unit monitoring the tag information in the second on-chip tag array to initiate speculative write back of selected cache lines based upon the quantity of dirty data in the selected cache lines while maintaining the data in the cache line and updating the tag information to indicate the selected cache line has non-dirty data.

14. The cache system of claim 12 wherein the speculative write back unit is operative to initiate a write back of a selected cache line independent of how recently the cache line was accessed.

15. The cache system of claim 12 wherein the tag information includes state information for the represented cache line and the speculative write back unit monitors the state information for each of a plurality of sub-blocks in each cache line and is operative to initiate a speculative write back of a cache line when more than a preselected number of sub-blocks in a cache line include dirty data.

16. The cache system of claim 15 wherein the preselected amount of dirty data is selected to be a fixed percentage of dirty data in the cache line.

17. The cache system of claim 15 wherein the preselected amount of dirty data is dynamically set based upon the time of last accesses to each cache line.

13. The cache system of claim 13 wherein the speculative write back unit is operative to initiate a write back of a selected cache line independent of frequency with which the selected cache line is accessed.

18. In a processor that executes coded instructions, a method for operation of a cache memory having a cache tag array comprising a plurality of entries wherein each entry stores tag information representing a line of data in the cache memory, the method comprising the steps of:

providing state information in the tag information indicating state of the represented cache line;

generating cache system access requests, each access request comprising an address identifying a memory location having data that is a target of the access;

performing a cache tag lookup by applying the address in an access to the cache tag array;

in response to the cache tag lookup, monitoring the state information of the cache tag entry corresponding to the access request to detect dirty data included in the represented cache line; and

initiating, in response to the monitoring step, a write back of the represented cache lines including more than a preselected amount of dirty data while maintaining the data in the represented cache lines and updating the state information to indicate the represented cache lines have non-dirty data.

19. The method of claim 18 wherein the step of generating cache system access requests further comprises initiating an inquiry of the cache tag array wherein the purpose of the inquiry is exclusively to monitor the state information.

20. The method of claim 18 wherein the initiated write back is given a low execution priority with respect to incoming cache system access requests.

21. The method of claim 20 further comprising the steps of:

using a least recently used mechanism independently of the initiated write back to select an entry in the cache to be written back.