Operating system notification of correctable error in computer information
First Claim
1. A computer system comprising:
- a processor;
a memory;
an error check circuit operably coupled to the memory and to the processor, the error check circuit detecting correctable errors in computer information, the error check circuit providing an error signal indicative of a detected correctable error;
a register circuit including;
a status register, the status register including a plurality of bit-fields, wherein the value of one of the bit-fields is responsive to the error signal;
an enable register including a plurality of bit-fields, each bit-field of the plurality of bit-fields of the enable register corresponds to a bit-field of the plurality of bit-fields of the status register, wherein one of the bit-fields of the enable register is corresponding to the one of the bit-fields of the status register whose value is responsive to the error signal;
wherein when the one of the bit-fields of the enable register contains a value indicating enablement, an interrupt to the processor is generated in response to the register circuit receiving the error signal.
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0 Petitions
Accused Products
Abstract
A computer system utilizing the Advance Configuration and Power Interface (ACPI) Standard to notify an ACPI compliant operating system of a detected correctable error. The computer system includes and error check circuit that detects correctable and non correctable errors in computer information flowing between the processor and a RAM. The error correction circuit provides a CE signal in response to detecting a correctable error. The computer system includes a register block circuit, that when enabled, generates an SCI to the processor in response to receiving the SCI. The processor accesses a status register of the SCI to determine that the error signal was sent. An ACPI driver of the operating system interprets ACPI control methods to direct the processor to perform the functions of the control method to obtain an address and syndrome of the information unit having the detected correctable error.
54 Citations
29 Claims
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1. A computer system comprising:
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a processor; a memory; an error check circuit operably coupled to the memory and to the processor, the error check circuit detecting correctable errors in computer information, the error check circuit providing an error signal indicative of a detected correctable error; a register circuit including; a status register, the status register including a plurality of bit-fields, wherein the value of one of the bit-fields is responsive to the error signal; an enable register including a plurality of bit-fields, each bit-field of the plurality of bit-fields of the enable register corresponds to a bit-field of the plurality of bit-fields of the status register, wherein one of the bit-fields of the enable register is corresponding to the one of the bit-fields of the status register whose value is responsive to the error signal; wherein when the one of the bit-fields of the enable register contains a value indicating enablement, an interrupt to the processor is generated in response to the register circuit receiving the error signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer system comprising:
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a processor, the processor executing code for the implementation of an operating system that implements an advanced configuration and power interface (ACPI) standard; a memory; an error check circuit operably coupled to the memory and to the processor, the error check circuit capable of detecting correctable errors in computer information, the error check circuit providing an error signal indicative of a detected correctable error; a register block circuit compatible with the ACPI standard, the register block circuit including a plurality of inputs for receiving event signals indicating that a type of ACPI event has occurred or is active, in response to receiving the error signal, the register block circuit, when enabled, providing an output signal to notify the operating system of the detected correctable error. - View Dependent Claims (15, 17, 18, 19)
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16. The computer system of 15 wherein the operating system includes an ACPI driver, wherein the operating system interpreting a control method includes the ACPI driver interpreting the control method.
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20. A computer system comprising:
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a processor, the processor executing code for the implementation of an operating system that implements an advanced configuration and power interface (ACPI) standard; a memory; an error check circuit operably coupled to the memory and to the processor, the error check circuit capable of detecting correctable errors in computer information, the error check circuit providing an error signal indicative of a detected correctable error; a register block circuit compatible with the ACPI standard, in response to receiving the error signal, the register block circuit, when enabled, providing an output signal to notify the operating system of the detected correctable error, wherein the register block circuit providing the output signal to notify the operating system causes the generation of an interrupt to the processor, wherein in response, the processor accesses the register block circuit to determine that the output signal was provided in response to the register block circuit receiving the error signal, wherein the operating system is notified of the detected correctable error.
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21. A method for notifying a computer system operating system implementing an advanced configuration and power interface (ACPI) standard of a detected correctable error comprising:
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detecting a correctable error in computer information and providing an indication thereof in a bit-field of a status register of a register block circuit including a plurality of inputs for receiving event signals indicating that a type of ACPI event has occurred or is active; generating an interrupt to a processor implementing an operating system if a bit-field of an enable register of the register block circuit corresponding to the bit-field of the status register indicates enablement; accessing the status register to determine that the interrupt was generated in response to the detection of a correctable error. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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Specification