Methods of reducing proximity effects in lithographic processes
First Claim
1. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
- defining a desired spacing between a main feature which is to reside on the mask and which is to be transferred onto the substrate and a pair of adjacent proximity effects-correcting features disposed on opposing sides of the main feature; and
after said defining, adjusting dimensions of the main feature relative to the pair of proximity effects-correcting features to achieve a desired transferred main feature dimension.
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Abstract
Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
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Citations
35 Claims
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1. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
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defining a desired spacing between a main feature which is to reside on the mask and which is to be transferred onto the substrate and a pair of adjacent proximity effects-correcting features disposed on opposing sides of the main feature; and after said defining, adjusting dimensions of the main feature relative to the pair of proximity effects-correcting features to achieve a desired transferred main feature dimension. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
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defining a desired spacing between a main feature which is to reside on the mask and which is to be transferred onto the substrate and a pair of adjacent sub-resolution features disposed on opposing sides of the main feature, the main feature having parallel edges; and moving each of the edges of the main feature relative to a respective adjacent one of the pair of sub-resolution features to achieve a desired transferred main feature dimension. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
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defining a plurality of main features which are to appear on the mask and be transferred onto a substrate, the main features having width dimensions; defining a desired spacing between a pair of sub-resolution features disposed on opposing sides of one of the main features and the one of the main features; changing a width dimension of the one main feature and not changing any dimensions of the pair of sub-resolution features; and forming a plurality of patterned main features on the substrate using the mask, said plurality of main features having substantially common patterned width dimensions. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
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defining a plurality of main features which are to appear on the mask at least some of which having width dimensions effective to form main feature patterns over a substrate with width dimensions which are no greater than a minimum photolithographic feature size from which the integrated circuitry is fabricated, one of the main features being spaced from other main features a distance which is effective to form a patterned main feature over the substrate which is spaced from other patterned main features over the substrate a distance which is greater than the minimum photolithographic feature size, the one main feature having a pair of edges defining a first width dimension; defining a desired spacing between the one main feature and each of a pair of proximity effects-correcting features, each of the pair to appear on the mask adjacent to opposing sides of the one main feature; and after said defining of the desired spacing, moving one of the opposing edges of the one main feature to define a second width dimension which is different from the first width dimension, moving enabling a patterned main feature to be formed on the substrate corresponding to the one main feature to have a width dimension which is no greater than the minimum photolithographic feature size. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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Specification