Methods of forming power semiconductor devices having merged split-well body regions therein

• US 6,121,089 A
• Filed: 06/05/1998
• Issued: 09/19/2000
• Est. Priority Date: 10/17/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Zeng, Jun, Wheatley, Carl Franklin Jr.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/092,334
• Time in Patent Office: 837 Days
• Field of Search: 438/299, 438/301, 438/303, 438/305, 438/306, 438/527, 438/549, 438/268, 438/270
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Methods of forming power semiconductor devices having merged split-well body regions include the steps of forming a semiconductor substrate containing a drift region of first conductivity type (e.g., N-type) therein extending to a first face thereof. First and second split-well body regions of second conductivity type (e.g., P-type) may also be formed at spaced locations in the drift region. First and second source regions of first conductivity type are also formed in the first and second split-well body regions, respectively. A central body/contact region of second conductivity type is also formed in the drift region, at a location intermediate the first and second split-well body regions. The central body/contact region preferably forms non-rectifying junctions with the first and second split-well body regions and a P-N rectifying junction with the drift region at a central junction depth which is less than the maximum well junction depths of the split-well body regions. First and second insulated gate electrodes may also be formed on the first face, opposite respective portions of the first and second split-well regions. Proper choice of drift region resistivity and implant conditions can be used to form a preferred dumbbell-shaped body region and move the location of breakdown within the device to a location which facilitates decoupling of device characteristics. A drift region extension of relatively high conductivity can also be provided along the bottom of the central body region to further limit the degree of coupling between device characteristics.

Claims

1. A method of forming a semiconductor switching device, comprising the steps of:

forming a semiconductor substrate containing a drift region of first conductivity type therein extending to a face thereof;

forming first and second split-well body regions of second conductivity type at spaced locations in the drift region, by driving split-well body region dopants into the drift region to achieve first and second maximum well junction depths for the first and second split-well body regions, respectively;

forming a first source region of first conductivity type in the first split-well body region;

forming a central body region of second conductivity type in the drift region at a location intermediate the first and second split-well body regions, by driving central body region dopants into the first and second split-well body regions and into the drift region to achieve a central junction depth which is less than the first and second maximum well junction depths;

forming an insulated gate electrode on the substrate, opposite the first split-well body region; and

forming a drift region extension of first conductivity type that forms a first P-N junction with the central body region by selectively implanting profile modification dopants of first conductivity type through the central body region and into the drift region using an implant mask that blocks the profile modification dopants from being implanted into a channel region extending along an interface between the first split-well body region and the insulated gate electrode.

2. The method of claim 1, wherein a first degree of abruptness in doping profile at the first P-N junction between the central body region and the drift region extension is greater than a second degree of abruptness in doping profile at a second P-N junction between the first split-well region and the drift region at the first maximum well junction depth.

3. The method of claim 2, further comprising the step of forming a trench in the substrate that has a sidewall which defines an interface with the first split-well body region and the first source region and a bottom which defines an interface with the drift region;

and wherein said step of forming an insulated gate electrode comprises forming an insulated gate electrode in the trench.

4. The method of claim 1, further comprising the step of forming a trench in the substrate;

and wherein said step of forming an insulated gate electrode comprises forming an insulated gate electrode in the trench.

5. The method of claim 3, wherein the trench has a sidewall which defines an interface with the first split-well body region and the first source region and a bottom which defines an interface with the drift region.

6. The method of claim 1, wherein said step of forming an insulated gate electrode comprises the steps of:

forming a gate insulating layer on the face; and

forming a patterned gate conductive layer on the gate insulating layer, opposite the face.

7. The method of claim 6, wherein said step of forming first and second split-well body regions comprises the step of implanting split-well body region dopants of second conductivity type into the face, using the patterned gate conductive layer as an implant mask;

and wherein said step of forming a first source region comprises implanting source region dopants of first conductivity type into the face, using the patterned gate conductive layer as an implant mask.

8. The method of claim 7, wherein said step of implanting split-well body region dopants of second conductivity precedes said step of implanting source region dopants of first conductivity type.

9. The method of claim 7, further comprising the step of forming an exclusion layer on the face;

wherein said step of implanting split-well body region dopants of second conductivity type comprises implanting dopants of second conductivity type into the face to define first and second preliminary split-well body regions in the drift region, using the exclusion layer as an implant mask; and

wherein said step of implanting source region dopants of first conductivity type comprises implanting source region dopants of first conductivity type into the face to define first and second preliminary source regions in the drift region, using the exclusion layer as an implant mask.

10. The method of claim 9, wherein said step of forming a central body region comprises the steps of:

forming a first spacer on a sidewall of the patterned gate conductive layer; and

implanting contact region dopants of second conductivity type into the first and second preliminary source regions to define a preliminary central body region in the drift region, using the first spacer as an implant mask.

11. The method of claim 10, wherein said step of forming a central body region comprises the steps of:

forming a second spacer, thicker than the first spacer, on the sidewall of the patterned gate conductive layer; and

implanting contact region dopants of second conductivity type into the preliminary central body region, using the second spacer as an implant mask.

12. The method of claim 10, wherein said step of forming a drift region extension comprises implanting profile modification dopants of first conductivity type through the central body region, using the patterned gate conductive layer as an implant mask.

13. The method of claim 11, wherein said step of forming a drift region extension comprises implanting profile modification dopants of first conductivity type through the central body region using the second spacer as an implant mask.

14. A method of forming a semiconductor switching device, comprising the steps of:

forming a substrate containing an semiconductor drift region of first conductivity type therein extending to a face thereof;

forming a mask having first and second spaced apart openings therein when viewed in transverse cross-section, on the face;

forming first and second split-well body regions at first and second spaced apart locations in the drift region, respectively, by implanting split-well body region dopants of second conductivity type at a first dose level through the first and second openings in the mask and into the drift region and then diffusing the implanted split-well body region dopants to achieve first and second maximum well junction depths for the first and second split-well body regions, respectively;

forming first and second source regions in the first and second split-well body regions, respectively, by implanting source region dopants of first conductivity type through the first and second openings in the mask and into the drift region;

forming a body/contact region by implanting body region dopants of second conductivity type at a second dose level, greater than the first dose level, into a portion of the drift region extending between the first and second spaced apart locations, and then diffusing the implanted body region dopants into the first and second split-well body regions and drift region to achieve a body/drift region junction depth which is less than the first and second maximum well junction depths;

forming an insulated gate electrode on the substrate, opposite the first splitwell body region; and

forming a drift region extension of first conductivity type that forms a first P-N junction with the body/contact region by selectively implanting profile modification dopants of first conductivity type through the body/contact region and into the drift region using an implant mask that covers the insulated gate electrode and blocks a first interface between the insulated gate electrode and the first split-well body region from being exposed to the implanted profile modification dopants.

15. The method of claim 14, wherein a first degree of abruptness in doping profile at the first P-N junction between the body/contact region and the drift region extension is greater than a second degree of abruptness in doping profile at a second P-N junction between the first split-well region and the drift region at the first maximum well junction depth.

16. The method of claim 15, further comprising the step of forming first and second trenches in the substrate;

wherein said step of forming an insulated gate electrode comprises forming first and second insulated gate electrodes in the first and second trenches, respectively, wherein the first trench has a sidewall which defines the first interface; and

wherein the second trench has a sidewall which defines a second interface between the second split-well body region and the second insulated gate electrode.

17. The method of claim 15, wherein said step of forming mask comprises the steps of forming a polysilicon conductive layer on the face, patterning the polysilicon conductive layer to define an opening therein and forming an exclusion layer in the opening;

and wherein said step of implanting body region dopants of second conductivity type at a second dose level is preceded by the step of removing the exclusion layer.

18. The method of claim 15, wherein said step of implanting split-well body region dopants precedes said step of implanting source region dopants.

19. A method of forming a semiconductor switching device, comprising the steps of:

forming a semiconductor substrate containing a drift region of first conductivity type therein extending to a face thereof;

forming first and second split-well body regions of second conductivity type having first and second maximum well junction depths, respectively, at spaced apart locations in the drift region;

forming a first source region of first conductivity type in the first split-well body region;

forming a central body region of second conductivity type in the drift region at a location intermediate the first and second split-well body regions, the central body region having a central junction depth which is less than the first and second maximum well junction depths;

forming an insulated gate electrode on the substrate, opposite the first split-well body region; and

forming a drift region extension of first conductivity type that forms a first P-N junction with the central body region and a non-rectifying junction with the drift region by selectively implanting profile modification dopant of first conductivity type into the drift region using an implant mask that covers the insulated gate electrode and blocks an interface between the insulated gate electrode and the first split-well body region from being exposed to the implanted profile modification dopants.

20. The method of claim 19, wherein a first degree of abruptness in doping profile at the first P-N junction between the central body region and the drift region extension is greater than a second degree of abruptness in doping profile at a second P-N junction between the first split-well region and the drift region at the first maximum well junction depth.

21. The method of claim 20, further comprising the step of forming a trench in the substrate;

wherein the trench has a sidewall which defines an interface with the first split-well body region and the first source region and a bottom which defines an interface with the drift region; and

wherein said step of forming an insulated gate electrode comprises forming an insulated gate electrode in the trench.

22. The method of claim 19, further comprising the step of forming a trench in the substrate;

and wherein said step of forming an insulated gate electrode comprises forming an insulated gate electrode in the trench.

23. The method of claim 19, wherein said step of forming an insulated gate electrode comprises the steps of forming a gate insulating layer on the face and forming a patterned gate conductive layer on the gate insulating layer, opposite the face;

wherein said step of forming first and second split-well body regions comprises the step of implanting split-well body region dopants of second conductivity type into the face, using the patterned gate conductive layer as an implant mask;

wherein said step of forming a first source region comprises implanting source region dopants of first conductivity type into the face, using the patterned gate conductive layer as an implant mask; and

wherein said step of implanting split-well body region dopants of second conductivity precedes said step of implanting split-well body region dopants of first conductivity type.

24. The method of claim 23, further comprising the step of forming an exclusion layer on the face;

wherein said step of implanting split-well body region dopants of second conductivity type comprises implanting split-well body region dopants of second conductivity type into the face to define first and second preliminary split-well body regions in the drift region, using the exclusion layer as an implant mask; and

wherein said step of implanting source region dopants of first conductivity type comprises implanting source region dopants of first conductivity type into the face to define first and second preliminary source regions in the drift region, using the exclusion layer as an implant mask.

25. A method of forming a semiconductor switching device, comprising the steps of:

forming a substrate containing a semiconductor drift region of first conductivity type therein;

forming a body region of second conductivity type that extends in the drift region and forms a first P-N junction therewith;

forming a source region of first conductivity type that extends in the body region and forms a second P-N junction therewith;

forming an insulated gate electrode that extends on a surface of the substrate and opposite a portion of the body region which acts as a channel region of second conductivity type when the switching device is biased in a forward on-state mode of operation; and

forming a drift region extension of first conductivity type that extends from the drift region to a third P-N rectifying junction with the body region, by selectively implanting profile modification dopants of first conductivity type through a portion of the body region and into the drift region using an implant mask that blocks the channel region of second conductivity type from being compensated by the implanted profile modification dopants of first conductivity type.

26. The method of claim 25, wherein a degree of abruptness on the drift region side of the first P-N junction is less than a degree of abruptness on the drift region extension side of the third P-N junction.

27. The method of claim 25, wherein the drift region extends to a face of the substrate;

and wherein the insulated gate electrode is formed on the face.

28. The method of claim 27, wherein the implant mask covers the insulated gate electrode.

29. The method of claim 25, wherein the substrate comprises a trench therein;

wherein the drift region extends to a sidewall of the trench; and

wherein the channel region extends to the sidewall of the trench.

30. The method of claim 29, wherein the implant mask covers the insulated gate electrode.

31. The method of claim 25, wherein application of a gate voltage of sufficient magnitude to the insulated gate electrode induces formation of an inversion-layer channel in the channel region when the switching device is biased in the forward on-state mode.

32. A method of forming a semiconductor switching device, comprising the steps of:

forming a substrate containing a semiconductor drift region of first conductivity type therein, a body region of second conductivity type in the drift region and a source region of first conductivity type in the body region;

forming an insulated gate electrode that extends on a surface of the substrate and defines an interface with the base region; and

forming a drift region extension of first conductivity type that extends from the drift region to a P-N rectifying junction with the body region, by selectively implanting profile modification dopants of first conductivity type through a portion of the body region and into the drift region using an implant mask that blocks the profile modification dopants from being implanted into a portion of the body region that extends along the interface between the body region and the insulated gate electrode.