Programmable logic datapath that may be used in a field programmable device

• US 6,121,791 A
• Filed: 06/30/1999
• Issued: 09/19/2000
• Est. Priority Date: 06/13/1997
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Malleable Technologies, Inc. (Microchip Technology Incorporated)
• Inventors: Abbott, Curtis
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/343,389
• Time in Patent Office: 447 Days
• Field of Search: 326/37-41
• US Class Current: 326/39
• CPC Class Codes: G06F 7/575 Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A method and apparatus for providing a programmable logic datapath that may be used in a field programmable device. According to one aspect of the invention, a programmable logic datapath is provided that includes a plurality of logic elements to perform various (Boolean) logic operations. The programmable logic datapath further includes circuitry to selectively route and select operand bits between the plurality of logic elements (operand bits is used hereinafter to refer to input bits, logic operation result bits, etc., that may be generated within the logic datapath). In one embodiment, by providing control bits concurrently with operand bits to routing and selection (e.g., multiplexing) circuitry, the programmable logic datapath of the invention can provide dynamic programmability to perform a number of logic operations on inputs of various lengths on a cycle-by-cycle basis.

Claims

1. A field programmable logic device comprising:

a decoder; and

a programmable logic datapath coupled to receive a plurality of control signals from said decoder and having a plurality of inputs, said programmable logic datapath including,

a rearrangement circuit to selectively coupled said plurality of inputs to different ones of a plurality of outputs; and

a plurality of reduction networks, each coupled to said plurality of outputs, to selectively perform logic operations on data provided at said plurality of outputs.

2. The field programmable logic device of claim 1, wherein said rearrangement circuit includes a plurality of multiplexers to selectively route and duplicate different ones of said plurality of inputs to said plurality of outputs.

3. The field programmable logic device of claim 1, wherein said decoder includes:

a memory addressable by inputs to said decoder, said memory for storing or having stored therein a plurality of sets of control signals, each set of control signals when applied to said programmable logic datapath causing said programmable logic datapath to perform a different function.

4. The field programmable logic device of claim 1 further including:

an input array;

a register bank; and

a selector coupled to said input array and said register bank, said selector to selectively provide said plurality of inputs to said programmable logic datapath from one or both of said input array and said register bank based on control signals provided by said decoder.

5. The field programmable logic device of claim 1, wherein each of said plurality of reduction networks includes:

at least a first and second level of logic circuits each having a plurality of logic circuit inputs, each of said first and second level of logic circuits providing a plurality of logic circuit outputs that each represent a different logic operation performed on data provided at said plurality of logic circuit inputs; and

an alignment circuit interposed between said first and second levels of logic circuits to selectively route different ones of said plurality of logic circuit outputs of said first level of logic to said plurality of logic circuit inputs of said second level of logic based on the control signals.

6. The field programmable logic device of claim 5, wherein each of said plurality of reduction networks also includes:

a transposition circuit to selectively interchange data being routed between said first and second level of logic circuits in said reduction network with data being routed between a first and second level of logic circuits in a different reduction network.

7. The field programmable logic device of claim 5, wherein each of said plurality of reduction networks also includes:

a negation circuit to selectively complement data being routed between said first and second level of logic circuits in said reduction network.

8. The field programmable logic device of claim 5, wherein each of said plurality of reduction networks also includes:

a subset selection circuit coupled to receive data based on said plurality of outputs of said rearrangement circuit, said subset selection circuit to selectively provide different sets of the data to each of said plurality of logic circuit inputs of said first level of logic circuits.

9. The field programmable logic device of claim 1, wherein said decoder can provide different sets of said plurality of control signals on a cycle-by-cycle basis.

10. The field programmable logic device of claim 1, wherein said plurality of reduction networks each provides one or two outputs bits that collectively are the output of said programmable logic datapath.