High frequency CMOS clock recovery circuit
First Claim
1. A complementary metal-oxide semiconductor (CMOS) clock recovery circuit for synchronizing a clock with data, comprising:
- a master-slave flip-flop having a clock input, a non-clock input, a data input, and an output;
a latch having a data input, a clock input, a non-clock input, and an output, the output of the master-slave flip-flop being connected to the data input of the latch;
a first exclusive-or gate having a first input, a second input, and an output, the data being connected to the first input and the output of the master-slave flip flop being connected to the second input;
a second exclusive-or gate having a first input, a second input, and an output, the output of the master-slave flip flop being connected to the first input and the output of the latch being connected to the second input;
means connected to the output of the first exclusive-or gate and connected to the output of the second exclusive-or gate for producing a difference signal representative of the difference between the average voltage of the output of the first exclusive-or gate and the average voltage of the output of the second exclusive-or gate; and
a clock having an input connected to the output of the difference signal producing means, and clock and non-clock outputs connected, respectively, to the clock and non-clock inputs of the master-slave flip flop, wherein the non-clock output is the inversion of the clock output.
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Abstract
A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.
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Citations
16 Claims
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1. A complementary metal-oxide semiconductor (CMOS) clock recovery circuit for synchronizing a clock with data, comprising:
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a master-slave flip-flop having a clock input, a non-clock input, a data input, and an output; a latch having a data input, a clock input, a non-clock input, and an output, the output of the master-slave flip-flop being connected to the data input of the latch; a first exclusive-or gate having a first input, a second input, and an output, the data being connected to the first input and the output of the master-slave flip flop being connected to the second input; a second exclusive-or gate having a first input, a second input, and an output, the output of the master-slave flip flop being connected to the first input and the output of the latch being connected to the second input; means connected to the output of the first exclusive-or gate and connected to the output of the second exclusive-or gate for producing a difference signal representative of the difference between the average voltage of the output of the first exclusive-or gate and the average voltage of the output of the second exclusive-or gate; and a clock having an input connected to the output of the difference signal producing means, and clock and non-clock outputs connected, respectively, to the clock and non-clock inputs of the master-slave flip flop, wherein the non-clock output is the inversion of the clock output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A monolithic complementary metal-oxide semiconductor (CMOS) integrated circuit (IC), comprising:
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one or more circuits, at least one of the circuits comprising a CMOS clock recovery circuit, the CMOS clock recovery circuit including; a master-slave flip-flop having a data input, a clock input, a non-clock input, and an output; a latch having a data input, a clock input, a non-clock input, and an output, the output of the master-slave flip flop being connected to the data input of the latch; a first exclusive-or gate having a first input, a second input, and an output, the data being connected to the first input and the output of the master-slave flip flop being connected to the second input; a second exclusive-or gate having a first input, a second input, and an output, the output of the master-slave flip flop being connected to the first input and the output of the latch being connected to the second input; means connected to the output of the first exclusive-or gate and connected to the output of the second exclusive-or gate for producing a difference signal representative of the difference between the average voltage of the output of the first exclusive-or gate and the average voltage of the output of the second exclusive-or gate; and a clock having an input connected to the difference signal producing means, and clock and non-clock outputs connected, respectively, to the clock and non-clock inputs of the master-slave flip flop, wherein the non-clock output is the inversion of the clock output. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification