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High frequency CMOS clock recovery circuit

  • US 6,121,804 A
  • Filed: 08/27/1998
  • Issued: 09/19/2000
  • Est. Priority Date: 08/27/1998
  • Status: Expired due to Term
First Claim
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1. A complementary metal-oxide semiconductor (CMOS) clock recovery circuit for synchronizing a clock with data, comprising:

  • a master-slave flip-flop having a clock input, a non-clock input, a data input, and an output;

    a latch having a data input, a clock input, a non-clock input, and an output, the output of the master-slave flip-flop being connected to the data input of the latch;

    a first exclusive-or gate having a first input, a second input, and an output, the data being connected to the first input and the output of the master-slave flip flop being connected to the second input;

    a second exclusive-or gate having a first input, a second input, and an output, the output of the master-slave flip flop being connected to the first input and the output of the latch being connected to the second input;

    means connected to the output of the first exclusive-or gate and connected to the output of the second exclusive-or gate for producing a difference signal representative of the difference between the average voltage of the output of the first exclusive-or gate and the average voltage of the output of the second exclusive-or gate; and

    a clock having an input connected to the output of the difference signal producing means, and clock and non-clock outputs connected, respectively, to the clock and non-clock inputs of the master-slave flip flop, wherein the non-clock output is the inversion of the clock output.

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