Universal duty cycle adjustment circuit
First Claim
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1. A circuit for adjusting the duty cycle of an input signal, comprising:
- a divide-by-two circuit having an input coupled to receive the input signal;
a switched current source circuit having an input coupled to an output of the divide-by-two circuit, and an output coupled to an integrating capacitor;
a slicer having a first input coupled to the integrating capacitor and a second input coupled to a reference signal;
a logic circuit configured to combine an output of the slicer with the output of the divide-by-two circuit to generate an output signal having a frequency substantially equal to the frequency of the input signal.
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Abstract
A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.
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Citations
19 Claims
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1. A circuit for adjusting the duty cycle of an input signal, comprising:
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a divide-by-two circuit having an input coupled to receive the input signal; a switched current source circuit having an input coupled to an output of the divide-by-two circuit, and an output coupled to an integrating capacitor; a slicer having a first input coupled to the integrating capacitor and a second input coupled to a reference signal; a logic circuit configured to combine an output of the slicer with the output of the divide-by-two circuit to generate an output signal having a frequency substantially equal to the frequency of the input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for adjusting the duty cycle of an input signal comprising the steps of:
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applying the input signal to a divide-by-two circuit; generating a triangular signal by charging and discharging a capacitor in response to an output of the divide-by-two circuit; generating a square-wave signal by comparing the triangular signal with a reference signal; and doubling the frequency of the square-wave signal by logically combining the square-wave signal with the output of the divide-by-two circuit. - View Dependent Claims (13, 14)
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15. A duty cycle adjustment circuit comprising:
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an edge triggered flip flop coupled as a divide-by-two circuit and having an input coupled to receive an input signal; a switched current source circuit coupled to the edge triggered flip flop and configured to charge and discharge an integrating capacitor in response to complementary outputs of the flip flop; a comparator having a first input coupled to the integrating capacitor and a second input coupled to a first reference signal; and a logic circuit configured to combine an output of the comparator with an output of the divide-by-two circuit to generate an output signal having a frequency substantially equal to the frequency of the input signal. - View Dependent Claims (16, 17, 18, 19)
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Specification