Universal duty cycle adjustment circuit

• US 6,121,805 A
• Filed: 10/08/1998
• Issued: 09/19/2000
• Est. Priority Date: 10/08/1998
• Status: Expired due to Term

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: Exar Corporation (Maxlinear Incorporated)
• Inventors: Tso, Vincent S., Thamsirianunt, Manop
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US09/169,181
• Time in Patent Office: 712 Days
• Field of Search: 327/172, 327/173, 327/174, 327/175, 327/176, 327/131, 327/115, 327/336, 375/238, 375/239
• US Class Current: 327/175
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.

Claims

1. A circuit for adjusting the duty cycle of an input signal, comprising:

a divide-by-two circuit having an input coupled to receive the input signal;

a switched current source circuit having an input coupled to an output of the divide-by-two circuit, and an output coupled to an integrating capacitor;

a slicer having a first input coupled to the integrating capacitor and a second input coupled to a reference signal;

a logic circuit configured to combine an output of the slicer with the output of the divide-by-two circuit to generate an output signal having a frequency substantially equal to the frequency of the input signal.

2. The circuit of claim 1 wherein the divide-by-two circuit comprises an edge triggered flip flop.

3. The circuit of claim 2 wherein the switched current source circuit comprises current sources and switches that operate in response to the output of the divide-by-two circuit to charge or discharge the integrating capacitor.

4. The circuit of claim 3 wherein the switched current source circuit comprises:

a charging current source;

a charging switch coupled between the charging current source and the integrating capacitor, and having a control terminal coupled to the divide-by-two circuit;

a discharging current source; and

a discharging switch coupled between the discharging current source and the integrating capacitor, and having a control terminal coupled to the divide-by-two circuit.

5. The circuit of claim 3 further comprising a pair of dc biasing resistors coupled between high and low power supplies and the output of the switched current source circuit.

6. The circuit of claim 3 wherein the slicer is a comparator and the logic circuit performs an exclusive OR function.

7. The circuit of claim 6 wherein a negative input of the comparator couples to the integrating capacitor, and a positive input of the comparator couples to the reference voltage.

8. The circuit of claim 1 further comprising a matching delay circuit having an identical slicer inserted between the output of the divide-by-two circuit and the logic circuit.

9. The circuit of claim 1 further comprising:

an ac coupling capacitor coupled between the integrating capacitor and the first input of the slicer; and

a dc biasing resistor coupled between the first input of the slicer and the reference voltage.

10. The circuit of claim 3 wherein a power supply voltage to the circuit provides a first voltage level and wherein the value of the reference voltage is set to be substantially equal to half the first voltage level.

11. The circuit of claim 3 wherein the reference voltage is set to a value to generate a square-wave at the output of the slicer having a phase shifted 90 degrees with respect to the output of the divide-by-two circuit.

12. A method for adjusting the duty cycle of an input signal comprising the steps of:

applying the input signal to a divide-by-two circuit;

generating a triangular signal by charging and discharging a capacitor in response to an output of the divide-by-two circuit;

generating a square-wave signal by comparing the triangular signal with a reference signal; and

doubling the frequency of the square-wave signal by logically combining the square-wave signal with the output of the divide-by-two circuit.

13. The method of claim 12 wherein the step of doubling the frequency of the square-wave signal comprises a step of performing an exclusive OR logical function between the square-wave signal and the output of the divide-by-two circuit.

14. The method of claim 13 wherein the step of generating a square-wave signal generates a square-wave signal having a phase shifted 90 degrees as compared to that of a signal at the output of the divide-by-two circuit.

15. A duty cycle adjustment circuit comprising:

an edge triggered flip flop coupled as a divide-by-two circuit and having an input coupled to receive an input signal;

a switched current source circuit coupled to the edge triggered flip flop and configured to charge and discharge an integrating capacitor in response to complementary outputs of the flip flop;

a comparator having a first input coupled to the integrating capacitor and a second input coupled to a first reference signal; and

a logic circuit configured to combine an output of the comparator with an output of the divide-by-two circuit to generate an output signal having a frequency substantially equal to the frequency of the input signal.

16. The duty cycle adjustment circuit of claim 15 wherein the switched current source circuit comprises:

a first current source coupled to the integrating capacitor via a first switch;

and

a second current source coupled to the integrating capacitor via a second switch.

17. The duty cycle adjustment circuit of claim 16 wherein the first switch is an MOS transistor having a gate terminal coupled to one output of the divide-by-two circuit, and the second switch is an MOS transistor having a gate terminal coupled to a complementary output of the divide-by-two circuit.

18. The duty cycle adjustment circuit of claim 15 wherein a second reference signal couples to the first input of the comparator.

19. The duty cycle adjustment circuit of claim 18 wherein a difference between the first reference signal and the second reference signal adjusts a duty cycle of the output signal.