DLL calibrated phase multiplexer and interpolator
First Claim
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1. A delay interpolation circuit comprising:
- a phase interpolator calibrator that takes adjacent coarse phase signals from a voltage controlled oscillator (VCO) and uses closed loop feedback to create a reference current that is used to bias a digital-to-analog converter DAC such that the full range of the DAC causes a current controlled delay cell to span a delay equal to the phase difference between adjacent coarse phase signals in a linear manner;
a delay interpolator that delays a clock signal output received from a phase multiplexer by an integer multiple N of a predefined phase delay, clock signal output delay being calibrated by the phase interpolator calibrator;
a delay adjuster connected to the delay interpolator for providing the value of N to the delay interpolator;
a delay selector that responds to a phase difference signal corresponding to the phase difference between an incoming data signal and a reference signal by providing corresponding first and second control signals, the first control signal being provided to the delay adjuster for use in determining the value of N; and
a coarse phase selector that responds to the second control signal by providing a coarse phase select signal to the phase multiplexer, the coarse phase select signal causing the phase multiplexer to select the clock signal from among a plurality of coarse phase-separated clock signals provided as inputs to the phase multiplexer.
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Abstract
A programmable phase adjuster spans a clock signal'"'"'s period with N linearly distributed phase steps. The resulting phase adjust resolution is finer than that of an inverter delay for a given process. Enhancement of the phase resolution of a phase picker CRM architecture enables use of the architecture for recovering clock signals from high data rate data streams in a way that minimizes power and area and allows optimization for multi-channel applications.
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Citations
1 Claim
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1. A delay interpolation circuit comprising:
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a phase interpolator calibrator that takes adjacent coarse phase signals from a voltage controlled oscillator (VCO) and uses closed loop feedback to create a reference current that is used to bias a digital-to-analog converter DAC such that the full range of the DAC causes a current controlled delay cell to span a delay equal to the phase difference between adjacent coarse phase signals in a linear manner; a delay interpolator that delays a clock signal output received from a phase multiplexer by an integer multiple N of a predefined phase delay, clock signal output delay being calibrated by the phase interpolator calibrator; a delay adjuster connected to the delay interpolator for providing the value of N to the delay interpolator; a delay selector that responds to a phase difference signal corresponding to the phase difference between an incoming data signal and a reference signal by providing corresponding first and second control signals, the first control signal being provided to the delay adjuster for use in determining the value of N; and a coarse phase selector that responds to the second control signal by providing a coarse phase select signal to the phase multiplexer, the coarse phase select signal causing the phase multiplexer to select the clock signal from among a plurality of coarse phase-separated clock signals provided as inputs to the phase multiplexer.
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Specification
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Current AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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Original AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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InventorsGaudet, Brian
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Primary Examiner(s)Zweizig, Jeffrey
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Application NumberUS09/080,860Time in Patent Office855 DaysField of Search327/231, 327/233, 327/236, 327/295, 327/298, 327/403, 327/407US Class Current327/231CPC Class CodesH03K 5/131 Digitally controlledH03L 7/0814 the phase shifting device b...H03L 7/0818 the controlled phase shifte...
