Apparatus and method for removing offset in a gain circuit

• US 6,121,831 A
• Filed: 05/12/1999
• Issued: 09/19/2000
• Est. Priority Date: 05/12/1999
• Status: Active Grant

• Current Assignee: Level One Communications, Inc. (Intel Corporation)
• Original Assignee: Level One Communications, Inc. (Intel Corporation)
• Inventors: Mack, Michael Peter
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/310,607
• Time in Patent Office: 496 Days
• Field of Search: 330/9, 330/51, 330/254, 327/307
• US Class Current: 330/9
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection

Abstract

An offset-removing gain circuit where the detected offset is independent of the gain of the circuit. The gain circuit includes a differential amplifier transfer circuit with an input and a output, an integrator connected to the output of the differential amplifier transfer circuit through a first impedance, and a second impedance connecting an output of the integrator to the input of the differential amplifier. The impedances may include resistors, capacitors or combinations thereof. The circuit may further include a switched capacitor circuit, where a plurality of capacitors are connected between input and output terminals using switches, whereby the capacitance of the switched capacitor circuit is altered by the switches to remove offset at the integrator output without changing the frequency response thereof.

Claims

1. An offset-removing gain circuit comprising:

a first circuit having a first transfer function to provide a gain of the circuit; and

a second circuit having a second transfer function, coupled to the first circuit, to provide an integrator output to be fed back to the first circuit;

the first and second circuits being arranged and configured to be capable of producing a plurality of different gains while allowing a frequency response of the circuit to remain unaffected.

2. The circuit according to claim 1, wherein the first circuit further comprises a first and second impedance devices, coupled to a first differential amplifier, for modifying the gain of the first circuit, wherein the first and second impedance devices operate to produce a product of first and second impedances that are selectable to provide the different gains of the first differential amplifier.

3. The circuit according to claim 2, wherein the second circuit further comprises a second differential amplifier with an input, an output and a plurality of impedances, wherein the plurality of impedances include a third impedance and a fourth impedance which are selected to remove offset at the integrator output without changing the frequency response of the circuit.

4. The circuit according to claim 3, wherein at least one of the impedances includes a resistor.

5. The circuit according to claim 3, wherein at least one of the impedances includes a capacitor.

6. The circuit according to claim 3, wherein at least one of the impedances includes a switched capacitor circuit, the switched capacitor circuit allowing selection of the gains of the first differential amplifier and allowing the frequency response of the circuit to remain unaffected.

7. The circuit according to claim 6, wherein the switched capacitor circuit includes:

first and second positive terminals, and first and second negative terminals;

a first capacitor connected between the first positive terminal and the second positive terminal;

a second capacitor connected between the first positive terminal and the second positive terminal, parallel to the first capacitor;

a third capacitor connected between a first switch and the second positive terminal;

a fourth capacitor connected between a second switch and the second positive terminal;

a fifth capacitor connected between the first negative terminal and the second negative terminal;

a sixth capacitor connected between the first negative terminal and the second negative terminal, parallel to the fifth capacitor;

a seventh capacitor connected between a third switch and the second negative terminal; and

an eighth capacitor connected between a fourth switch and the second negative terminal;

wherein the first switch connects the third capacitor to the first positive terminal, parallel to the second capacitor, or to the first negative terminal, the second switch connects the fourth capacitor to the first positive terminal, parallel to the second capacitor, or to ground, the third switch connects the seventh capacitor to the first negative terminal, parallel to the sixth capacitor, or to the first positive terminal and the fourth switch connects the eighth capacitor to the first negative terminal, parallel to the sixth capacitor, or to ground.

17. The circuit according to claim 3, wherein a product of the third impedance and the fourth impedance remains the same when the different gains are provided.

8. A CMOS transceiver on a single device, including:

conditioning circuitry conditioning a received signal;

an offset-removing gain circuit comprising;

a first circuit having a first transfer function to provide a gain of the circuit;

a second circuit having a second transfer function, coupled to the first circuit, to provide an integrator output to be fed back to the first circuit;

the first and second circuits being arranged and configured to be capable of producing a plurality of different gains while allowing a frequency response of the circuit to remain unaffected; and

processing circuitry processing an output signal from the offset-removing gain circuit for receipt outside the device.

9. The CMOS transceiver according to claim 8, wherein the first circuit further comprises a first and second impedance devices, coupled to a first differential amplifier, for modifying the gain of the first circuit, wherein the first and second impedance devices operate to produce a product of first and second impedances that are selectable to provide different gains of the first differential amplifier.

10. The CMOS transceiver according to claim 9, wherein the second circuit further comprises a second differential amplifier with an input, an output and a plurality of impedances, wherein the plurality of impedances include a third impedance and a fourth impedance which are selected to remove offset at the integrator output without changing the frequency response of the circuit.

11. The CMOS transceiver according to claim 8, wherein the conditioning circuitry includes an anti-aliasing filter.

12. The CMOS transceiver according to claim 10, wherein at least one of the impedances includes a switched capacitor circuit, the switched capacitor circuit allowing selection of the gains of the differential amplifier and allowing the frequency response of the circuit to remain unaffected.

18. The CMOS transceiver according to claim 10, wherein a product of the third impedance and the fourth impedance remains the same when the different gains are provided.

19. The method according to claim 10, wherein a product of the third impedance and the fourth impedance remains the same when the gain is changed.

13. A method of removing offset from a signal while amplifying, the method comprising:

feeding an input signal into a differential amplifier via a first impedance device having a first impedance;

feeding an output of the differential amplifier through a feedback path including a second impedance device having a second impedance;

feeding the output signal from the differential amplifier though a third impedance device having a third impedance into an integrator;

feeding an inverted integrated signal from the integrator through a fourth impedance device having a fourth impedance into the differential amplifier; and

changing the first impedance of the first impedance device to change a gain of the differential amplifier while selecting the third and fourth impedances of the third and fourth impedance devices to remove an offset at the integrator output and allow the frequency response of the circuit to remain unaffected.

14. The method according to claim 13, wherein a ratio of the first and fourth impedances of the first and fourth impedance devices remain constant.

15. The method according to claim 13, further comprising conditioning the input signal prior to feeding the input signal into the differential amplifier.

16. The method according to claim 15, wherein conditioning the input signal includes feeding the input signal through an anti-aliasing filter.