Semiconductor memory device with a column redundancy occupying a less chip area

• US 6,122,194 A
• Filed: 01/26/2000
• Issued: 09/19/2000
• Est. Priority Date: 12/29/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hwi-Taek, Park, Jong-Min
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/491,846
• Time in Patent Office: 237 Days
• Field of Search: 365/185.09, 365/200, 365/185.17, 365/185.11, 371/10.2, 371/10.3
• US Class Current: 365/185.09
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

A semiconductor memory device is provided which comprises a mat having a plurality of sectors for storing information of data; and a redundancy circuit for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited. Each of the sectors comprises a main memory cell array and the redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells. Each sector further comprises a first column selector for selecting one of the main columns of each bit segment in response to first column address signals; a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals; and a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals. Furthermore, each sector has a plurality of sense amplifiers for sensing and amplifying stored data in corresponding main column and; redundant column thus selected; and a plurality of multiplexers each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal.

Claims

1. A semiconductor memory device comprising:

a mat having a plurality of sectors for storing information, one of the sectors having a main memory cell array that comprises plural word lines and plural column lines, and having a redundancy memory cell array;

a redundancy selection circuit that comprises a plurality of redundancy flag generators and a plurality of redundancy selection signal generators connected to the mat, such that when a selected sector in the mat has defective columns of memory cells, other sectors in the mat are repaired in association with the defective columns of the one sector by use of the same redundancy selection circuit;

wherein said plurality of redundancy flag generators and redundancy selection signal generators comprise fuse means respectively.

2. The semiconductor memory device according to claim 1, wherein said main memory cell array and said redundancy cell array share said word lines.