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Semiconductor memory device and method for relieving defective memory cells

  • US 6,122,207 A
  • Filed: 03/16/1999
  • Issued: 09/19/2000
  • Est. Priority Date: 04/30/1998
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • plural memory cell arrays, each memory cell array having plural memory cell groups, each of said memory cell groups being connected via a local bus to a cell array global bus line commonly shared by each of said memory cell groups of each memory cell array;

    a redundancy memory cell array with a redundancy cell array global bus line, said redundancy memory cell array having plural redundancy memory cell groups, each of said redundancy memory cell groups being connected via a local bus to said redundancy cell array global bus line,said redundancy memory cell array being shared by at least two memory cell arrays; and

    a control circuit connected to said redundancy cell array and said two memory cell arrays for transmitting data for one or more memory cells of said redundancy memory cell groups in place of data for one or more defective memory cells in any of said plural memory cell groups of said two memory cell arrays.

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