Semiconductor memory device and method for relieving defective memory cells

• US 6,122,207 A
• Filed: 03/16/1999
• Issued: 09/19/2000
• Est. Priority Date: 04/30/1998
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nobutoki, Tomoko, Koshikawa, Yasuji, Mine, Kouji
• Primary Examiner(s): Tran, Andrew
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/268,994
• Time in Patent Office: 553 Days
• Field of Search: 365/200, 365/201, 365/230.03, 365/230.5, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.

Claims

1. A semiconductor memory device comprising:

plural memory cell arrays, each memory cell array having plural memory cell groups, each of said memory cell groups being connected via a local bus to a cell array global bus line commonly shared by each of said memory cell groups of each memory cell array;

a redundancy memory cell array with a redundancy cell array global bus line, said redundancy memory cell array having plural redundancy memory cell groups, each of said redundancy memory cell groups being connected via a local bus to said redundancy cell array global bus line,

said redundancy memory cell array being shared by at least two memory cell arrays; and

a control circuit connected to said redundancy cell array and said two memory cell arrays for transmitting data for one or more memory cells of said redundancy memory cell groups in place of data for one or more defective memory cells in any of said plural memory cell groups of said two memory cell arrays.

2. The semiconductor memory device of claim 1, wherein:

said control circuit is connected to said redundancy memory cell array and said two memory cell arrays by a first section comprising said redundancy cell array global bus line and two cell array global bus lines, each one of said two cell array global bus lines corresponding to one of said two memory cell arrays.

3. The semiconductor memory device of claim 2, wherein:

said redundancy cell array global bus line is switchable connected to each local bus line of said redundancy cell array; and

each of said two cell array global bus lines is switchable connected to each local bus line of said corresponding memory cell array.

4. The semiconductor memory device of claim 1, wherein:

said redundancy cell array global bus line and two of said cell array global bus lines connect to said control circuit to form a first section for transmitting data through mutually different of said redundancy cell array global bus line and said two cell array global bus lines to one of said two memory cell arrays and said redundancy memory cell array; and

said control circuit is further connected to a second section for transmitting data for both said redundancy memory cell array and one of said two memory cell arrays through a common bus.

5. The semiconductor memory device of claim 1, wherein:

each of said redundancy memory cell groups is connectable to every input/output terminal associated with said two memory cell arrays.

6. The semiconductor memory device of claim 1 wherein:

each of said memory cell groups and said redundancy memory cell groups is connectable to a common input/output terminal.

7. The semiconductor memory device of claim 4, wherein:

a first memory cell group of a first of said two memory cell arrays is connected to a first input/output terminal and a second memory cell group of a second of said two memory cell arrays is commonly connected to said first input/output terminal;

when memory cells of said first memory cell group are replaced with memory cells of said redundancy memory cell array, data of said memory cells of said redundancy memory cell array is controlled to be transmitted through a bus common to said first memory cell group in said second section; and

when memory cells of said second memory cell group are replaced with memory cells of said redundancy memory cell array, data of said memory cells of said redundancy memory cell array is controlled to be transmitted through a bus common to said second of said memory cell groups in said second section.

8. The semiconductor memory device of claim 4, wherein:

a first of said memory cell groups is connected to a first input/output terminal and a second of said memory cell groups is connected to a second input/output terminal;

when memory cells of said first of said memory cell groups are replaced with memory cells of said redundancy memory cell array, data of said memory cells of said redundancy memory cell array is controlled to be transmitted through a bus common to said first of said memory cell groups in said second section; and

when memory cells of said second of said memory cell groups are replaced with memory cells of said redundancy memory cell array, data of said memory cells of said redundancy memory cell array is controlled to be transmitted through a bus common to said second of said memory cell groups in said second section.

9. A semiconductor memory device comprising:

a bus selecting circuit coupled to a redundancy cell array global bus line, to a first memory cell array global bus line, and to a second memory cell array global bus line;

said first memory cell array global bus line being further switchable connected at plural points to a first memory cell array, said first memory cell array having plural memory cell groups, each of said memory cell groups being connected via a local bus to said first memory cell array global bus line;

said second memory cell array global bus line being further switchable connected at plural points to a second memory cell array, said second memory cell array having plural memory cell groups, each of said memory cell groups being connected via a local bus to said second memory cell array global bus line;

said redundancy memory cell array global bus line being further connected at plural points to a redundancy memory cell array, said redundancy memory cell array having plural redundancy memory cell groups, each of said redundancy memory cell groups being connected via a local bus to said redundancy memory cell array global bus line;

said redundancy memory cell array being shared by said first and second memory cell arrays; and

said bus selecting circuit cell being controllable for transmitting data for one or more memory cells of said redundancy memory cell groups in place of data for one or more defective memory cells in any of said plural memory cell groups of said first and second memory cell arrays.

10. The semiconductor memory device of claim 9, wherein:

said bus selecting circuit comprises a first data amplifier, a first write amplifier, a second data amplifier, and a second write amplifier,

said first data amplifier and said first write amplifier are connected to said redundancy cell array global bus line and to said first memory cell array global bus line,

said second data amplifier and said second write amplifier are connected to said redundancy cell array global bus line and to said second memory cell array global bus line,

said first data amplifier and said first write amplifier are connected to a first input/output terminal, and

said second data amplifier and said second write amplifier are connected to second input/output terminal.

11. The semiconductor memory device of claim 9, wherein:

said bus selecting circuit comprises a first data amplifier, a first write amplifier, a second data amplifier, and a second write amplifier,

said first data amplifier and said first write amplifier are connected to said redundancy cell array global bus line and to said first memory cell array global bus line,

said second data amplifier and said second write amplifier are connected to said redundancy cell array global bus line and to said second memory cell array global bus line, and

said first data amplifier, said first write amplifier, said second data amplifier, and said second write amplifier are connected to a common input/output terminal.

12. The semiconductor memory device of claim 9, wherein:

when memory cells of said first memory cell array are replaced with memory cells of said redundancy memory cell array, data of said redundancy memory cells is controlled to be transmitted through a bus common to said first memory cell array and said redundancy memory cell array, and

when memory cells of said second memory cell array are replaced with memory cells of said redundancy memory cell array, data of said redundancy memory cells is controlled to be transmitted through a bus common to said second memory cell array and said redundancy memory cell array.

13. The semiconductor memory device of claim 9, wherein:

when memory cells of said first memory cell array are replaced with memory cells of said redundancy memory cell array, data of said redundancy memory cells is controlled to be transmitted through a bus common to said first memory cell array, said second memory cell array, and said redundancy memory cell array, and

when memory cells of said second memory cell array are replaced with memory cells of said redundancy memory cell array, data of said redundancy memory cells is controlled to be transmitted through said bus common to said first memory cell array, said second memory cell array, and said redundancy memory cell array.

14. The semiconductor memory device of claim 13, wherein:

said redundancy memory cell array is located intermediate said first memory cell array and said second memory cell array.

15. A method for relieving defective memory cells in a semiconductor device, comprising the steps of:

providing a redundancy memory cell array corresponding to a plurality of memory cell arrays,

providing each of the plural memory cell arrays with plural memory cell groups connected to a local bus line, the local bus lines of each memory cell groups being switchable connected to a memory cell array global bus line;

providing a bus switching control connected to the memory cell array global bus line corresponding to each of the plural memory cell arrays and connected to the redundancy memory cell array via a redundancy memory cell array bus line; and

transmitting data for one or more memory cells of said redundancy memory cell array via said redundancy memory cell array bus line in place of data for one or more defective memory cells in any of said plurality of memory cell arrays.

16. The method of claim 15, comprising the further step of:

providing the bus switching control with a data path to each input/output terminal, which data path is common for data of the redundancy memory cell array and data of at least one of the plural memory cell arrays.

17. The method of claim 15, comprising the further steps of:

determining whether an input column address coincides with a column address of a defective column of one of the plural memory cell arrays; and

in the case where the input column address coincides with a defective column of one of the plural memory cell arrays, transmit data of the redundancy memory cell array in place of the data of said defective column through a bus common to the redundancy memory cell array and to the memory cell array corresponding to the defective column.

18. The method of claim 16, wherein the data path is provided common to the redundancy memory cell array and each of the plural memory cell arrays.

19. The method of claim 15, further comprising the step of positioning the redundancy cell array intermediate the memory cell arrays.

20. The method of claim 15, wherein:

the step of providing a bus switching control connected to the memory cell array global bus line corresponding to each of the plural memory cell arrays and connected to the redundancy memory cell array via a redundancy memory cell array bus line, includes providing a number of data and write amplifier units equal to the number of memory cell arrays,

wherein each of the data and write amplifier units are connected to connected to the redundancy memory cell array via the redundancy memory cell array bus line.