Fast, low power, write scheme for memory circuits using pulsed off isolation device

• US 6,122,211 A
• Filed: 12/09/1998
• Issued: 09/19/2000
• Est. Priority Date: 04/20/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morgan, Donald M., McLaury, Loren L.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/208,146
• Time in Patent Office: 650 Days
• Field of Search: 365/205, 365/149, 365/207, 365/189.01
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A circuit, for controlling a write operation during which data from data lines is written to a memory cell, is used with a memory cell of the type that is connected to a row line and a first column line. An amplifier is connected across the first column line and a column line complimentary to the first column line. The column lines have a capacitance associated therewith. The circuit includes a control circuit for generating switching control signals. Switches are provided which are positioned in the column lines and are responsive to the switching control signals for selectively isolating at least a portion of the column lines during a predetermined portion of the write operation.

Claims

1. A circuit connected to a data line, comprising:

a column line connected to the data line, said column line having a first portion and a second portion;

a dynamic memory cell connected to said column line;

an amplifier having a terminal connected to said column line, wherein said amplifier receives data from said data line, said data to be written to said memory cell; and

a switch having a first terminal, a second terminal, and a gate, terminal, said first terminal connected to said first portion of said column line, said second terminal connected to said second portion of said column line, and said gate terminal responsive to a switch control signal so that said switch isolates said amplifier from the data line before said amplifier is connected to said cell.

2. The circuit of claim 1, wherein said switch includes a transistor.

3. The circuit of claim 1, further comprising a row line connected to said cell.

4. The circuit of claim 1, wherein said cell is connected to said first portion of said column line.

5. The circuit of claim 1, wherein said amplifier is connected to said first portion of said column line.

6. The circuit of claim 1, further comprising a precharge circuit connected to said column line.

7. The circuit of claim 1, further comprising a second switch in said column line and connecting said cell to said amplifier along said column line.

8. The circuit of claim 1, further comprising a control circuit having an output terminal connected to said gate terminal of said switch.

9. The circuit of claim 8, wherein said control circuit includes a pulse generator.

10. The circuit of claim 1, wherein said amplifier includes a sense amplifier.

11. The circuit of claim 10, wherein said sense amplifier includes a P-sense amplifier.

12. The circuit of claim 10, wherein said sense amplifier includes an N-sense amplifier.

13. The circuit of claim 1, further comprising a second column connected to a second terminal of said amplifier.

14. The circuit of claim 13, wherein said first and said second column lines are complementary.

15. The circuit of claim 13, further comprising a second cell connected to said second column line.

16. The circuit of claim 13, wherein said second column line has a first portion and a second portion, further comprising a second switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said second column line and said second terminal connected to said second portion of said second column line.

17. The circuit of claim 15, wherein said cell and said second cell are connected to a row line.

18. The circuit of claim 16, further comprising a control circuit having an output terminal connected to said gate terminal of said second switch.

19. A circuit connected to a data line, comprising:

a column line connected to the data line, said column line having a first portion and a second portion;

a dynamic memory cell connected to said column line;

a control circuit having an output terminal;

an amplifier connected to said column line, wherein said amplifier receives data from said data line said data to be written to said memory cell; and

a switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said column line, said second terminal connected to said second portion of said column line, and said gate terminal connected to said output terminal of said control circuit so that said switch isolates said amplifier from the data line before said amplifier is connected to said cell.

20. The circuit of claim 19, wherein said switch includes a transistor.

21. A circuit connected to a data line, comprising:

a first column line connected to the data line, said first column line having a first portion and a second portion;

a second column line connected to the data line, said second column line having a first portion and a second portion;

a dynamic memory cell connected to said first column line;

an amplifier having a first terminal and a second terminal, said first terminal connected to said first column line and said second terminal connected to said second column line wherein said amplifier receives data from said data line said data is to be written to said memory cell;

a first switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said first column line, said second terminal connected to said second portion of said first column line, and said gate terminal responsive to a switch control signal so that said first switch isolates said amplifier from the data line before said amplifier is connected to said cell; and

a second switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said second column line, said second terminal connected to said second portion of said second column line, and said gate terminal responsive to said switch control signal.

22. The circuit of claim 21, wherein said first and second column lines are complementary.

23. A circuit connected to a data line, comprising:

a first column line connected to the data line, said first column line having a first portion and a second portion;

a second column line connected to the data line, said second column line having a first portion and a second portion;

a dynamic memory cell connected to said first column line;

a control circuit having an output terminal;

an amplifier having a first terminal and a second terminal, said first terminal connected to said first column line and said second terminal connected to said second column line wherein said amplifier receives data from said data line, said data to be written to said memory cell;

a first switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said first column line, said second terminal connected to said second portion of said first column line, and said gate terminal connected to said output terminal of said control circuit so that said first switch isolates said amplifier from the data line before said amplifier is connected to said cell; and

a second switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said second column line, said second terminal connected to said second portion of said second column line, and said gate terminal connected to said output terminal of said control circuit.

24. A dynamic memory device connected to a data line, comprising:

a first column line connected to the data line, said first column line having a first portion, a second portion, and a third portion;

a second column line connected to the data line, said second column line having a first portion, a second portion, and a third portion, said second column line complementary to said first column line;

a dynamic memory cell having a first terminal and a second terminal, said first terminal connected to a row line and said second terminal connected to said first column line;

a sense amplifier having a first terminal and a second terminal, said first terminal connected to said first column line and said second terminal connected to said second column line wherein said amplifier receives data from said data line, said data to be written to said memory cell;

a first transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said first column line, said second terminal connected to said second portion of said first column line, and said gate terminal responsive to a first switch control signal so that said first transistor disconnects said amplifier from the data line before said amplifier is connected to said cell;

a second transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said second portion of said first column line, said second terminal connected to said third portion of said first column line, and said gate terminal responsive to a second switch control signal so that said second transistor isolates said third portion of said first column line from said amplifier while said amplifier is connected to the data line;

a third transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said second column line, said second terminal connected to said second portion of said second column line, and said gate terminal responsive to said first switch control signal; and

a fourth transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said second portion of said second column line and said second terminal connected to said third portion of said second column line, and said gate terminal responsive to said second switch control signal.

25. The memory device of claim 24, further comprising a second dynamic memory cell having a first terminal and a second terminal, said first terminal connected to said row line and said second terminal connected to said second column line.

26. A dynamic memory device connected to a data line, comprising:

a first column line connected to the data line, said first column line having a first portion, a second portion, and a third portion;

a second column line connected to the data line, said second column line having a first portion, a second portion, and a third portion, said second column line complementary to said first column line;

a dynamic memory cell having a first terminal and a second terminal, said first terminal connected to a row line and said second terminal connected to said first column line;

a switch control circuit having a first output terminal and a second output terminal;

a sense amplifier having a first terminal and a second terminal, said first terminal connected to said first column line and said second terminal connected to said second column line, wherein said amplifier receives data from said data line, said data to be written to said memory cell;

a first transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said first column line, said second terminal connected to said second portion of said first column line, and said gate terminal connected to said first output terminal of said switch control circuit so that said first transistor disconnects said amplifier from the data line before said amplifier is connected to said cell;

a second transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said second portion of said first column line, said second terminal connected to said third portion of said first column line, and said gate terminal connected to said second output terminal of said switch control circuit so that said second transistor isolates said third portion of said first column line from said amplifier while said amplifier is connected to the data line;

a third transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said second column line, said second terminal connected to said second portion of said second column line, and said gate terminal connected to said first output terminal of said switch control circuit; and

a fourth transistor having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said second portion of said second column line, said second terminal connected to said third portion of said second column line, and said gate terminal connected to said second output terminal of said switch control circuit.

27. The memory device of claim 26, further comprising a second dynamic memory cell having a first terminal and a second terminal, said first terminal connected to said row line and said second terminal connected to said second column line.

28. A system, comprising:

a processor; and

a dynamic memory device responsive to said processor, said memory device including a circuit connected to a data line, said circuit including;

a column line connected to the data line, said column line having a first portion and a second portion;

a dynamic memory cell connected to said column line;

an amplifier connected to said column line wherein said amplifier receives data from said data line, said data to be written to said memory cell; and

a switch having a first terminal, a second terminal, and a gate terminal, said first terminal connected to said first portion of said column line, said second terminal connected to said second portion of said column line, and said gate terminal responsive to a switch control signal so that said switch isolates said amplifier from the data line before said amplifier is connected to said cell.