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Fast, low power, write scheme for memory circuits using pulsed off isolation device

  • US 6,122,211 A
  • Filed: 12/09/1998
  • Issued: 09/19/2000
  • Est. Priority Date: 04/20/1993
  • Status: Expired due to Term
First Claim
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1. A circuit connected to a data line, comprising:

  • a column line connected to the data line, said column line having a first portion and a second portion;

    a dynamic memory cell connected to said column line;

    an amplifier having a terminal connected to said column line, wherein said amplifier receives data from said data line, said data to be written to said memory cell; and

    a switch having a first terminal, a second terminal, and a gate, terminal, said first terminal connected to said first portion of said column line, said second terminal connected to said second portion of said column line, and said gate terminal responsive to a switch control signal so that said switch isolates said amplifier from the data line before said amplifier is connected to said cell.

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