Sense amplifier with feedbox mechanism

• US 6,122,212 A
• Filed: 05/01/1998
• Issued: 09/19/2000
• Est. Priority Date: 05/01/1998
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Wang, Chien-fan, Bui, John Henry
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US09/071,669
• Time in Patent Office: 872 Days
• Field of Search: 365/207, 365/208, 365/185.21, 365/189.07, 365/189.09, 365/210, 365/189.01, 365/185.01, 327/51, 327/53
• US Class Current: 365/207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

A sense amplifier for detecting a logic state of a memory cell includes a voltage amplifier, a current mirror, and a feedback circuit. The voltage amplifier couples to the memory cell and the current mirror. The feedback circuit couples to the current mirror and an input of the sense amplifier. The feedback circuit can be implemented with a transistor, a switch, a transmission gate, or the like. The feedback circuit is selectively enabled to quickly charge or discharge the voltage at the input of the sense amplifier to a trip voltage of the sense amplifier. Whether charging or discharging is performed is dependent on the voltage then existing at the input node. The amount of charging and discharging current can also be based on other circuit considerations, such as the required charge time, and so on. When the voltage at the input reaches a predetermined voltage range, the feedback circuit is disabled.

Claims

1. A sense amplifier comprising:

an input amplifier configured to receive and amplify a signal from a memory cell;

a first current mirror coupled to the input amplifier and configured to receive the amplified signal and generate at least one current signal, wherein each of the at least one current signal is related to the amplified signal by a respective gain factor; and

a feedback circuit operatively coupled to the input amplifier and the first current mirror, the feedback circuit configured to provide a feedback between an output of the first current mirror and an input of the input amplifier, and

wherein the feedback circuit is selectively enabled for a particular duration of time during a sensing operation.

2. The sense amplifier of claim 1, further comprising:

a reference current source coupled to the first current mirror and configured to provide a reference current.

3. The sense amplifier of claim 2, wherein the reference current source is configured to receive a signal from a dummy memory cell.

4. The sense amplifier of claim 1, wherein the feedback circuit is disabled when voltage at the input of the input amplifier falls within a particular voltage range.

5. The sense amplifier of claim 1, wherein a bias current of the first current mirror is set, in part, based on a conducting memory cell current.

6. The sense amplifier of claim 1, wherein a bias current of the first current mirror is set, in part, based on a trip voltage of the input amplifier.

7. The sense amplifier of claim 6, wherein the trip voltage of the sense amplifier is set at approximately 1.5 volts.

8. The sense amplifier of claim 1, wherein the feedback circuit is implemented with a MOS transistor.

9. The sense amplifier of claim 1, further comprising:

a buffer coupled to the output of the first current mirror.

10. The sense amplifier of claim 1, wherein the first current mirror is configured to provide a first current signal and a second current signal, wherein the first current signal is provided to the input amplifier and the second current signal is provided to a reference current source.

11. The sense amplifier of claim 1, further comprising:

a control circuit coupled to the feedback circuit and configured to generate a control signal for the feedback circuit, wherein the control signal disables the feedback circuit when voltage at the input of the input amplifier falls within a particular voltage range.

12. The sense amplifier of claim 1, wherein the input amplifier, the first current mirror, and the feedback circuit are implemented with MOS transistors.

13. An integrated circuit having an embedded memory that includes at least one sense amplifier of claim 1.

14. A memory circuit comprising at least one sense amplifier of claim 1.

15. A dynamic random access memory circuit comprising at least one sense amplifier of claim 1.

16. A sense amplifier comprising:

an input amplifier operative to receive and amplify a signal from a memory cell;

a first current mirror coupled to the input amplifier and configured to receive the amplified signal and generate at least one current signal;

a feedback circuit operatively coupled to an output of the first current mirror and an input of the input amplifier, wherein the feedback circuit is selectively enabled for a particular duration of time during a sensing operation;

a second current mirror coupled to the input amplifier and configured to sense whether voltage at the input of the input amplifier exceeds an upper threshold; and

a third current mirror coupled to the input amplifier and configured to sense whether the voltage at the input of the input amplifier falls below a lower threshold.

17. The sense amplifier of claim 16, further comprising:

a fourth current mirror coupled to the input amplifier and configured to sense whether the voltage at the input of the input amplifier exceeds a low threshold; and

wherein the feedback circuit is enabled when the voltage at the input of the input amplifier falls below the low threshold.

18. The sense amplifier of claim 16, wherein the feedback circuit is disabled when the voltage at the input of the input amplifier falls within a voltage range defined by the upper and lower thresholds.

19. The sense amplifier of claim 16, further comprising:

a buffer coupled to the first current mirror.

20. The sense amplifier of claim 16, wherein the feedback circuit is implemented with one or more MOS transistors.

21. The sense amplifier of claim 16, wherein the input amplifier, the first current mirror, and the feedback circuit are implemented with MOS transistors.

22. A sense amplifier for detecting a logic state of a memory cell comprising:

an input amplifier operative to receive and amplify a signal from the memory cell;

a first current mirror coupled to the input amplifier and configured to receive the amplified signal and generate at least one current signal, wherein each of the at least one current signal is related to the amplified signal by a respective gain factor and provided via a respective current path;

a reference current source coupled to a first current path of the first current mirror; and

a feedback circuit coupled to an input of the input amplifier and an output of the first current mirror, wherein the feedback circuit is selectively enabled for a particular duration of time during a sensing operation.

23. A memory device comprising:

a plurality of memory cells;

a plurality of sense amplifiers, each sense amplifier operatively and selectively coupled to a respective set of memory cells, wherein each sense amplifier includes a feedback circuit that couples between an output and an input of the sense amplifier;

at least one control circuit, each control circuit coupled to at least one associated sense amplifier and configured to generate a respective control signal for the feedback circuit within the at least one associated sense amplifier; and

a logic circuit coupled to the plurality of control circuits, the logic circuit configured to generate a read signal when voltages at the inputs of the plurality of sense amplifiers are each within a particular voltage range.

24. A method for sensing a logic state of a memory cell comprising:

receiving an input signal indicative of the logic state of the memory cell;

determining whether the input signal is within a particular range;

if the input signal is determined to be outside the particular range, pulling the input signal toward a trip voltage with a feedback signal; and

detecting the logic state of the memory cell based on the input signal, and

wherein the feedback signal is selectively enabled for a particular duration of time during a sensing operation.

25. The method of claim 24, wherein the feedback signal is generated based, in part, on a voltage of the input signal.

26. The method of claim 24, wherein the feedback signal is generated based, in part, on a conducting memory cell current.

27. The method of claim 24, wherein the feedback signal is generated based, in part, on a previously sensed logic state.

28. A method for sensing a logic state of a memory cell comprising:

receiving an input signal indicative of the logic state of the memory cell;

determining whether the input signal is within a particular range;

if the input signal is determined to be outside the particular range, pulling the input signal toward a trip voltage with a feedback signal, wherein the feedback signal is generated based, in part, on a conducting memory cell current and a voltage of the input signal;

amplifying the input signal with a particular gain;

detecting the amplified signal;

generating a sensed signal based on the detected signal, wherein the sensed signal is indicative of the sensed logic state of the memory cell; and

buffering the sensed signal to generate an output signal, and

wherein the feedback signal is selectively enabled for a particular duration of time during a sensing operation.

29. A sense amplifier comprising:

an input amplifier configured to receive and amplify an input signal;

a comparison circuit coupled to the input amplifier and configured to receive and compare the amplified signal with a reference signal;

a feedback circuit coupled to an output of the comparison circuit and an input of the input amplifier, wherein the feedback circuit is selectively enabled for a particular duration of time during a sensing operation;

a first sensing circuit coupled to the input amplifier and configured to sense whether voltage at the input of the input amplifier exceeds an upper threshold; and

a second sensing circuit coupled to the input amplifier and configured to sense whether the voltage at the input of the input amplifier falls below a lower threshold.

30. The sense amplifier of claim 29, further comprising:

a third sensing circuit coupled to the input amplifier and configured to sense whether the voltage at the iniput of the input amplifier exceeds a low threshold, and

wherein the feedback circuit is enabled when the voltage at the input of the input amplifier falls below the low threshold.

31. The sense amplifier of claim 29, wherein the comparison circuit is implemented with a current mirror.

32. The sense amplifier of claim 29, wherein the first and second sensing circuits are each implemented with a current mirror.

33. The sense amplifier of claim 29, further comprising:

a control circuit coupled to the feedback circuit and configured to generate a control signal for the feedback circuit, wherein the control signal disables the feedback circuit when the voltage at the input of the input amplifier falls within a particular voltage range.