IC chip tester using compressed digital test data and a method for testing IC chip using the tester

• US 6,122,761 A
• Filed: 08/26/1998
• Issued: 09/19/2000
• Est. Priority Date: 08/26/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sang Gon
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US09/140,448
• Time in Patent Office: 755 Days
• Field of Search: 714/724, 714/738, 714/718, 324/158.1, 324/73.1, 324/76.11
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

Disclosed are a tester for testing an IC chip using test data consisting of many test vectors and a method for testing an IC chip using the tester. The tester has a pin memory, a sequencer memory, and a driving part. The pin memory stores many data blocks. Each of the test blocks is a combination of one or more test vector, and is repeated at least one time in the test data. The sequencer memory stores information about a designation order of the test blocks for restoring the test data. The driving part drives the pin memory so that the test blocks stored therein are output successively according to the designation order stored in the sequencer memory. The tester does not require an additional CPU, and the programming therefor is simple.

Claims

1. A tester for testing an IC chip using test data consisting of a plurality of test vectors, the tester comprising:

a pin memory for storing a plurality of test blocks, the test blocks each of which is a combination of at least one test vector among the test vectors and is repeated at least one time in the test data;

a sequencer memory for storing information about a designation order of the test blocks for restoring the test data; and

a driving part for driving the pin memory so that the test blocks stored in the pin memory are output successively according to the designation order stored in the sequencer memory.

2. The tester for testing an IC chip as claimed in claim 1, wherein the sequencer memory comprises:

an address memory for storing initial addresses which are addresses of first test vectors of respective test blocks, according to the designation order; and

a length memory for storing information about the number of the test vectors in the test block designated by the initial address, according to the designation order.

3. The tester for testing an IC chip as claimed in claim 2, wherein the driving part comprises:

an address counter to which the initial address is input from the address memory, the address counter for designating addresses of the test vectors stored in the pin memory;

a length counter to which the information about the number of the test vectors is input from the length memory, the length counter for successively changing a value of the address counter as much as a value input thereto so that all of the test vectors in one test block are successively designated by the address counter; and

a program pointer for driving the address memory and the length memory so that next information in the address memory and the length memory are respectively input to the address counter and the length counter after the designation of all of the test vectors in one test block has been completed.

4. The tester for testing an IC chip as claimed in claim 1, wherein the pin memory comprises a plurality of RAMs, wherein the number of the RAMs is identical to that of bits of the test vector.

5. The tester for testing an IC chip as claimed in claim 1, further comprising a pin driver for converting the test data output from the pin memory to signals suitable for the IC chip.

6. A method for testing an IC chip using test data consisting of a plurality of test vectors, the method comprising the steps of:

determining a plurality of test blocks, the test blocks each of which is a combination of at least one test vector among the test vectors and is repeated at least one time in the test data;

setting a designation order of the test blocks for restoring the test data;

restoring the test data by outputting the test blocks successively according to the designation order;

inputting the restored test data to the IC chip; and

judging whether the IC chip is normal or not by comparing output data of the IC chip caused by the test data with reference data.