Method for making deep sub-micron mosfet structures having improved electrical characteristics
First Claim
1. A method for fabricating improved MOSFET devices on a semiconductor substrate having device areas comprising the steps of:
- depositing a first insulating layer and a second insulating layer and patterning to form openings for FET polysilicon gate electrodes over said device areas;
depositing and etching back a third insulating layer to form arc-shaped first sidewall spacers in said openings;
implanting an anti-punchthrough dopant in said substrate between said first sidewall spacers;
forming a gate oxide on said device areas in said openings;
depositing a polysilicon layer and polishing back to form polysilicon gate electrodes in said openings aligned over said gate oxide;
isotropically etching said second insulating layer, said first insulating layer, and said arc-shaped first sidewall spacers, leaving free-standing said polysilicon gate electrodes having a shape determined by said arc-shaped sidewall spacers, whereby said polysilicon gate electrodes gradually increase in width as a function of increasing height from said gate oxide;
ion implanting a dopant through said polysilicon gate electrodes to form graded, lightly doped source/drain areas adjacent to said gate oxide and concurrently doping said gate electrodes;
depositing and anisotropically etching back a fourth insulating layer to form second sidewall spacers and air spacers adjacent to said gate electrodes;
ion implanting source/drain con tact areas adjacent to said second sidewall spacers and concurrently doping said polysilicon gate electrodes;
depositing and annealing a metal layer to form a metal silicide on said polysilicon gate electrodes and on said source/drain contact areas and removing said metal that is unreacted to complete said MOSFET devices.
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Accused Products
Abstract
A method for making improved MOSFET structures is achieved. A Si3 N4 and a SiO2 layer are deposited and patterned to have openings for gate electrodes over device areas on a substrate. A second Si3 N4 layer is deposited and etched back to form arc-shaped sidewall spacers in the openings. An anti-punchthrough implant and a gate oxide are formed in the openings between the Si3 N4 sidewall spacers. A polysilicon layer is deposited and polished back to form gate electrodes. The SiO2 and the Si3 N4 layers, including the sidewall spacers, are removed to form free-standing gate electrodes that increase in width with height, and having arc-shaped sidewalls. An implant through the edges of the arc-shaped gate electrodes results in lightly doped source/drains that are graded both in junction depth and dopant concentration to reduce hot electron effects. A second SiO2 layer is deposited and etched back to form insulating sidewall spacers that include air spacers to reduce the gate-to-drain capacitance. Another implant is used to form source/drain contact areas. A salicide process is used which forms a silicide on the polysilicon gate electrodes and on the source/drain contact areas. The arc-shaped structure allows MOSFETs to be formed with reduced channel lengths while maintaining a wider silicide area on the gate electrodes for reduced resistance.
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Citations
28 Claims
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1. A method for fabricating improved MOSFET devices on a semiconductor substrate having device areas comprising the steps of:
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depositing a first insulating layer and a second insulating layer and patterning to form openings for FET polysilicon gate electrodes over said device areas; depositing and etching back a third insulating layer to form arc-shaped first sidewall spacers in said openings; implanting an anti-punchthrough dopant in said substrate between said first sidewall spacers;
forming a gate oxide on said device areas in said openings;depositing a polysilicon layer and polishing back to form polysilicon gate electrodes in said openings aligned over said gate oxide; isotropically etching said second insulating layer, said first insulating layer, and said arc-shaped first sidewall spacers, leaving free-standing said polysilicon gate electrodes having a shape determined by said arc-shaped sidewall spacers, whereby said polysilicon gate electrodes gradually increase in width as a function of increasing height from said gate oxide; ion implanting a dopant through said polysilicon gate electrodes to form graded, lightly doped source/drain areas adjacent to said gate oxide and concurrently doping said gate electrodes; depositing and anisotropically etching back a fourth insulating layer to form second sidewall spacers and air spacers adjacent to said gate electrodes; ion implanting source/drain con tact areas adjacent to said second sidewall spacers and concurrently doping said polysilicon gate electrodes; depositing and annealing a metal layer to form a metal silicide on said polysilicon gate electrodes and on said source/drain contact areas and removing said metal that is unreacted to complete said MOSFET devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for fabricating improved MOSFET devices on a semiconductor substrate having device areas comprising the steps of:
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depositing a first insulating layer composed of silicon nitride and a second insulating layer composed of silicon oxide, and patterning to form openings for FET gate electrodes over said device areas; depositing and etching back a third insulating layer composed of silicon nitride to form arc-shaped first sidewall spacers in said openings; implanting an anti-punchthrough dopant in said substrate between said first sidewall spacers;
forming a gate oxide on said device areas in said openings;depositing a polysilicon layer and polishing back to form gate electrodes in said openings aligned over said gate oxide; isotropically etching said second insulating layer, said first insulating layer, and said arc-shaped first sidewall spacers, leaving free-standing said polysilicon gate electrodes having a shape determined by said arc-shaped sidewall spacers, whereby said polysilicon gate electrodes gradually increase in width as a function of increasing height from said gate oxide; ion implanting a dopant through said gate electrodes to form graded, lightly doped source/drain areas adjacent to said gate oxide and concurrently doping said gate electrodes; depositing and anisotropically etching back a fourth insulating layer to form second sidewall spacers and air spacers adjacent to said gate electrodes; ion implanting source/drain contact areas adjacent to said second sidewall spacers and concurrently doping said gate electrodes; depositing and annealing a titanium metal layer to form a metal silicide on said polysilicon gate electrodes and on said source/drain contact areas and removing said metal that is unreacted to complete said MOSFET devices. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. An improved MOSFET device over device areas on a semiconductor substrate comprised of:
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polysilicon gate electrodes aligned over a gate oxide and an anti-punchthrough doped region in said substrate aligned under said gate oxide; said gate electrodes having arc-shaped sidewalls that increase outward with increasing height from said gate oxide and said arc-shaped sidewalls extending over lightly doped source/drain areas; lightly doped source and drains having increasing dopant concentration and increasing junction depth graded to extend away from edge of said gate oxide; insulating sidewall spacers extending vertically downward from top edge of said gate electrodes to said substrate that form air spacers between said insulating sidewall spacers and said arc-shaped sidewalls of said polysilicon gate electrodes; source/drain contacts in said substrate adjacent to outer portions of said insulating sidewall spacers; a metal silicide on top surface of said gate electrodes and on said source/drain contacts. - View Dependent Claims (26, 27, 28)
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Specification