Inverted dielectric isolation process

• US 6,124,179 A
• Filed: 01/30/1998
• Issued: 09/26/2000
• Est. Priority Date: 09/05/1996
• Status: Expired due to Fees

• Current Assignee: Fred W. Adamic Jr
• Original Assignee: Fred W. Adamic Jr
• Inventors: Adamic, Fred W. Jr.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US09/016,745
• Time in Patent Office: 970 Days
• Field of Search: 438/421, 438/459, 438/977, 438/FOR 485, 438/FOR 107, 438/309, 438/FOR 227
• US Class Current: 438/309
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.

Claims

1. A method of fabricating a circuit on a substrate, the method comprising:

doping a plurality of active regions of a device on the first side of the substrate;

forming insulated interconnects interconnecting the active regions of the device on the first side of the substrate;

forming a dielectric layer on the first side of the substrate overlying the insulated interconnects of the device;

bonding a support to the first side of the substrate overlying the dielectric layer thereby forming a composite structure;

removing a portion of the substrate on a second side of the substrate opposite the first side of the substrate so that only active regions of the device remain;

doping second-side regions of the device into the second side of the substrate; and

forming a second-side conductor on the second side of the substrate.

2. A method according to claim 1 wherein:

the device is an NPN transistor; and

the substrate has an N-type conductivity.

3. A method according to claim 1 wherein:

the device is a PNP transistor; and

the substrate has a P-type conductivity.

4. A method according to claim 1 wherein:

the device is a PNP transistor;

the substrate has an N-type conductivity;

the substrate includes a doped P-type conductivity region; and

the PNP transistor is formed in the doped P-type conductivity region.

5. A method according to claim 1 wherein:

the substrate is an epitaxial layer formed on a silicon wafer.

6. A method according to claim 1 further comprising:

etching isolation trenches that mutually separate and mutually electrically isolate a plurality of devices into the second side of the substrate.

7. A method according to claim 1 further comprising:

etching isolation trenches that mutually separate and mutually electrically isolate a plurality of devices into the second side of the substrate and extending fully through the substrate to the first side of the substrate.

8. A method according to claim 1 further comprising:

forming doped second-side regions of the device into the second side of the substrate to create same-conductivity-type ohmic regions and form low-resistance lateral collector lead-outs.

9. A method according to claim 1 further comprising:

forming doped second-side regions of the device into the second side of the substrate to create opposite-conductivity-type regions to construct four-layer devices such as silicon-controlled rectifiers.

10. A method according to claim 1 further comprising:

etching isolation trenches that mutually separate and mutually electrically isolate a plurality of devices into the second side of the substrate and extending fully through the substrate to the first side of the substrate;

wherein

the second-side conductor on the second side of the substrate extends into the isolation trenches and connects with an interconnect of the insulated interconnects on the first side of the substrate to form a frontside collector terminal.

11. A method according to claim 1 further comprising:

forming LOCOS isolation regions that mutually separate and mutually electrically isolate a plurality of devices into the second side of the substrate and extending fully through the substrate to the first side of the substrate.

12. A method according to claim 1 further comprising:

forming a bond layer to bond the support to the first side of the substrate;

depositing a bond interface metal layer between the bond layer and the support, the bond metal layer having a resistivity of less than approximately 15 microhms-cm and thermal conductivity greater than approximately 0.80 watts/cm-°

C.

13. A method according to claim 1 forming a vertical insulated gate bipolar transistor (IGBT) combining a double-diffused metal-oxide-semiconductor (DMOS) device and a bipolar emitter wherein:

the first-type conductivity is an N-type conductivity;

the second-type conductivity is a P-type conductivity;

the operation of forming a plurality of doped regions of a device on the first side of the substrate further includes;

forming a plurality of polysilicon gate regions connected in a connected mesh on the first side of the substrate;

forming a diffused, P-type body region as an enlarged base-width for a parasitic NPN device which is intrinsic to a double-diffused metal-oxide-semiconductor (DMOS) device on the first side of the substrate;

simultaneously doping a plurality of P-type body regions of the double-diffused metal-oxide-semiconductor (DMOS) device self-aligned with a selected polysilicon gate region of the plurality of polysilicon gate regions under an edge of the selected polysilicon gate region; and

simultaneously doping a plurality of N-type source regions of the double-diffused metal-oxide-semiconductor (DMOS) device partially penetrating into a respective P-type body region of the plurality of P-type body regions and self-aligned with a selected polysilicon gate region of the plurality of polysilicon gate regions; and

the operation of doping second-side regions of the device into the second side of the substrate further includes;

forming a P-type bipolar emitter on the exposed second side surface of the substrate.

14. A method of fabricating a bipolar device circuit having a plurality of devices including a first-type device and a second-type device, the second-type being complementary to the first type, the first-type device and second-type device having mutually similar operating characteristics and scalable sizes, the method comprising:

lightly doping a region of a second-type conductivity into a first side of a substrate having a first-type conductivity, the second-type conductivity being complementary to the first-type conductivity;

doping regions of the first-type device into the first side of the first-type conductivity substrate;

doping regions of the second-type device into the first side of the substrate in the region of second-type conductivity;

forming insulated interconnects interconnecting doped regions of the first-type device and doped regions of the second-type device on the first side of the substrate;

forming a dielectric layer on the first side of the substrate overlying the insulated interconnects of the first-type device and the second-type device;

bonding a support to the first side of the substrate overlying the dielectric layer thereby forming a composite structure;

removing a portion of the substrate on a second side of the substrate opposite the first side of the substrate so that only active regions of the first-type device and the second-type device remain;

doping second-side regions of the first-type device into the second side of the first-type conductivity substrate;

doping second-side regions of the second-type device into the second side of the substrate in the region of second-type conductivity;

forming a second-side conductor on the second side of the substrate.

15. A method according to claim 14 wherein:

the first-type device is an NPN transistor; and

the second-type device is a PNP transistor;

the NPN and PNP transistors being complementary and having a mutually similar structure.

16. A method according to claim 14 wherein:

the first-type conductivity substrate is an epitaxial layer formed on a silicon wafer.

17. A method according to claim 14 further comprising:

etching isolation trenches that separate and electrically isolate the first-type device from the second-type device into the second side of the substrate.

18. A method according to claim 14 further comprising:

etching isolation trenches that separate and electrically isolate the first-type device from the second-type device into the second side of the substrate and extending fully through the substrate to the first side of the substrate.

19. A method according to claim 14 further comprising:

doping second-side regions of the first-type device and the second-type device into the second side of the substrate with a first-type dopant and a second-type dopant respectively to create same-conductivity-type ohmic regions and form low-resistance lateral collector lead-outs.

20. A method according to claim 14 wherein the first-type conductivity substrate is a first epitaxial layer formed on a silicon wafer, the substrate having a low-voltage transistor region extending vertically through the substrate and a high-voltage transistor region extending vertically through the substrate horizontally distinct from the low-voltage transistor region, the method further comprising:

doping the low-voltage transistor region of the first-type conductivity substrate to form a buried layer of the first-type in the low-voltage transistor region;

depositing a second epitaxial layer on the first epitaxial layer, the second epitaxial layer vertically extending the high-voltage transistor region and the low-voltage transistor region, the second epitaxial layer being in the first-type conductivity; and

doping the low-voltage transistor region with an enhanced doping of the first-type conductivity on the first side of the substrate, the enhanced doping of the first type overlapping the buried layer;

etching isolation trenches separating and electrically-isolating the first-type device from the second-type device into the second side of the substrate;

forming the second-side conductor on the second side of the substrate into the isolation trenches, the buried layer making an ohmic contact with the second-side conductor at an isolation trench sidewall and forming a lateral collector leadout.