Metallization structure and method for a semiconductor device

• US 6,124,189 A
• Filed: 03/14/1997
• Issued: 09/26/2000
• Est. Priority Date: 03/14/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okumura, Katsuya, Watanabe, Toru, Hieda, Katsuhiko
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US08/818,079
• Time in Patent Office: 1,292 Days
• Field of Search: 438/586, 438/587, 438/257, 438/692, 438/740, 438/670, 438/234, 438/237, 438/299, 438/621, 438/643, 438/653, 438/633, 438/672, 438/677
• US Class Current: 438/586
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer. Subsequent steps include: removing the first insulating layer, thereby forming an unfilled region above the polysilicon layer; depositing a metal such as tungsten in the unfilled region and the contact hole; and polishing the deposited metal layer to planarize the upper surface of the metal with the upper surface of the second insulating layer.

Claims

1. A method for forming a metal-strapped polysilicon gate structure, comprising the steps of:

forming a gate dielectric layer on a surface of a substrate;

forming a polysilicon layer on said gate dielectric layer;

forming a masking layer on said polysilicon layer;

patterning said masking layer;

etching said polysilicon layer using said patterned masking layer as a mask to form a gate electrode;

depositing an insulating layer on said substrate;

removing said patterned masking layer, thereby forming an unfilled region above said gate electrode;

depositing a metal to fill in said unfilled region; and

planarizing the deposited metal such that an upper surface of said metal is substantially level with an upper surface of said insulating layer.

2. The method according to claim 1, wherein said metal is tungsten.

3. The method according to claim 1, wherein the deposited metal is planarized by a chemical mechanical polishing process.

4. The method according to claim 1, wherein said metal is deposited using a blanket deposition method.

5. The method of claim 1, further including the step of forming an adhesion layer on said gate electrode, the step of depositing said metal including depositing said metal on said adhesion layer.

6. The method of claim 5, wherein the step of forming the adhesion layer is performed after the step of removing said patterned masking layer.

7. The method of claim 5, wherein said adhesion layer comprises titanium nitride.

8. The method of claim 7, wherein said metal is tungsten.

9. The method of claim 1, wherein the step of depositing said metal includes depositing said metal to at least completely fill in said unfilled region.

10. The method of claim 1, wherein the step of depositing said metal includes depositing said metal to overflow said unfilled region onto a surface of said insulating layer.

11. The method of claim 10, further including the step of adjusting a surface of said metal to be coplanar with said insulating layer.

18. The method according to claim 11, wherein said insulating spacers are formed of silicon dioxide.

12. A method for forming a metal-strapped polysilicon gate structure and a metal contact structure, comprising the steps of:

forming a gate dielectric layer on a surface of a substrate;

forming a polysilicon layer on said gate dielectric layer;

forming a masking layer on said polysilicon layer;

patterning said masking layer;

etching said polysilicon layer using said patterned masking layer as a mask to form a gate electrode;

implanting ions in the surface of said substrate using said patterned masking layer and said gate electrode as an implantation mask to thereby form spaced apart source/drain regions;

depositing an insulating layer on said substrate;

forming a contact hole in said insulating layer for contacting at least one of said source/drain regions;

removing said patterned masking layer to form an unfilled region above said gate electrode; and

depositing a metal to fill in said unfilled region and said contact hole.

13. The method according to claim 12, further comprising the step of polishing said insulating layer to planarize an upper surface of said insulating layer.

14. The method according to claim 12, further comprising the step of polishing said deposited metal to planarize an upper surface of said metal.

15. The method according to claim 12, wherein said metal is tungsten.

16. The method according to claim 12, wherein said masking layer is a silicon nitride layer.

17. The method according to claim 12, further comprising the step of forming insulating spacers on sidewalls of said patterned masking layer and said gate electrode prior to implanting ions in the surface of said silicon substrate.

19. The method according to claim 12, further comprising the step of forming a silicide layer on said source/drain regions.

20. A method according to claim 12, wherein said insulating layer is a silicon dioxide layer.

21. The method according to claim 12, wherein said contact hole aligns to said gate electrode in lithography.

22. The method according to claim 12, further comprising the step of forming a contact diffusion region after forming said contact hole.

23. The method according to claim 12, wherein said masking layer is removed using a wet etching process.

24. The method according to claim 12, wherein said metal is deposited using a selective deposition method in which said metal is deposited selectively in said unfilled region and said contact hole.

25. The method according to claim 12, wherein said metal is deposited using a blanket deposition method.

26. The method according to claim 13, wherein said polishing step is performed using a chemical mechanical polishing process.

27. The method of claim 12, further including the step of forming an adhesion layer on said gate electrode, the step of depositing said metal including depositing said metal on said adhesion layer.

28. The method of claim 27, wherein the step of forming the adhesion layer is performed after the step of removing said patterned masking layer.

29. The method of claim 27, wherein said adhesion layer comprises titanium nitride.

30. The method of claim 29, wherein said metal is tungsten.

31. The method of claim 12, wherein the step of depositing said metal includes depositing said metal to at least completely fill in said unfilled region.

32. The method of claim 12, wherein the step of depositing said metal includes depositing said metal to overflow said unfilled region onto a surface of said insulating layer.

33. The method of claim 32, further including the step of adjusting a surface of said metal to be coplanar with said insulating layer.

34. A method of forming a gate electrode comprising the steps of:

forming a structure on a semiconductor substrate which is insulatively spaced from a channel region between source/drain regions formed on a surface of said semiconductor substrate, said structure including a first conductive layer and a cap layer formed on said first conductive layer;

depositing an insulating layer on said semiconductor substrate and said structure;

planarizing an upper surface of said insulating layer using said cap layer as a stopper;

removing said cap layer to form an opening above said first conductive layer of said structure;

depositing a conductive material in said opening; and

planarizing an upper surface of said conductive material using said insulating layer as a stopper.

35. The method of claim 34, further including the step of forming an adhesion layer on said conductive layer, the step of depositing said conductive material including depositing said conductive material on said adhesion layer.

36. The method of claim 35, wherein the step of forming the adhesion layer is performed after the step of removing said cap layer.

37. The method of claim 35, wherein said adhesion layer comprises titanium nitride.

38. The method of claim 37, wherein said conductive material is tungsten.

39. The method of claim 34, wherein the step of depositing said conductive material includes depositing said conductive material to at least completely fill said opening.

40. The method of claim 34, wherein the step of depositing said conductive material includes depositing said conductive material to overflow said opening onto the upper surface of said insulating layer.

41. A method of simultaneously forming a gate electrode and a contact, comprising the steps of:

forming a structure on a semiconductor substrate which is insulatively spaced from a channel region between source/drain regions formed on a surface of said semiconductor substrate, said structure including a first conductive layer and a cap layer formed on said first conductive layer;

depositing an insulating layer on said semiconductor substrate and said structure;

planarizing an upper surface of said insulating layer using said cap layer as a stopper;

forming contact holes to expose at least one of said source/drain regions;

removing said cap layer to form an opening above said conductive layer of said structure;

depositing a conductive material to simultaneously fill said opening and said contact holes; and

planarizing an upper surface of said conductive material using said insulating layer as a stopper.

42. The method of claim 41, further including the step of forming an adhesion layer on said conductive layer, the step of depositing said conductive material including depositing said conductive material on said adhesion layer.

43. The method of claim 42, wherein the step of forming the adhesion layer is performed after the step of removing said cap layer.

44. The method of claim 42, wherein said adhesion layer comprises titanium nitride.

45. The method of claim 44, wherein said conductive material is tungsten.

46. The method of claim 41, wherein the step of depositing said conductive material includes depositing said conductive material to at least completely fill each of said opening and said contact holes.

47. The method of claim 41, wherein the step of depositing said conductive material includes depositing said conductive material to overflow each of said opening and said contact holes onto the upper surface of said insulating layer.