Non-volatile trench semiconductor device having a shallow drain region

• US 6,124,608 A
• Filed: 12/18/1997
• Issued: 09/26/2000
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang William, Sun, Yu, Wollesen, Donald L.
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/992,961
• Time in Patent Office: 1,013 Days
• Field of Search: 257/315, 257/321, 257/330, 257/322, 257/332, 438/259
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region. During ion implantation, a region containing an impurity of the first conductivity type is formed at the intersection of each trench and the substrate surface to prevent shorting between the source/drain region and gate electrodes.

Claims

1. A semiconductor device comprising:

a substrate having a main surface and containing an impurity of a first conductivity type;

first and second trenches formed in the substrate, each trench comprising;

(a) first and second side surfaces intersecting the main surface at edges and extending into the substrate; and

(b) a bottom surface joining the first side surface at a first corner and the second side surface at a second corner within the substrate;

a substantially U-shaped tunnel dielectric layer lining each trench;

a substantially U-shaped floating gate electrode on the tunnel dielectric layer in each trench;

a dielectric layer on each floating gate electrode and extending on the edges and a portion of the main surface terminating in side surfaces; and

a control gate electrode having;

(a) a first portion extending below the main surface on the dielectric layer in each trench; and

(b) a second portion extending on each dielectric layer on the main surface terminating in side surfaces;

sidewall spacers on the side surfaces of the dielectric layers and second portion of the control gate electrode;

a drain region containing an impurity of a second conductivity type extending from the main surface into the substrate to a first depth between the second side surface of the first trench and the first side surface of the second trench;

a channel region containing an impurity of the first conductivity type extending between the second side surface of the first trench and first side surface of the second trench deeper into the substrate than the drain region;

a first source region, containing an impurity of the second conductivity type, and extending from the main surface into the substrate to a second depth, greater than the first depth, along the first side surface of the first trench;

an impurity region of the first conductivity type extending from the main surface at each trench edge of each trench into the substrate and entirely within a source/drain region; and

a second source region, containing an impurity of the second conductivity type, and extending from the main surface into the substrate to a third depth, greater than the first depth, along the second side surface of the second trench, wherein each tunnel dielectric layer and floating gate electrode has an upper surface substantially flush with the main surface of the substrate, and the second and third depths are substantially the same.

2. The semiconductor device according to claim 1, wherein the first and second source regions extend into the substrate to a depth less than the trench corners.

3. The semiconductor device according to claim 1, wherein:

the first source region extends into the substrate below the first side surface along the first corner and along the bottom surface of the first trench;

the second source region extends into the substrate below the second side surface along the second corner and along the bottom surface of the second trench; and

the channel region extends below the second corner of the first trench and below the first corner of the second trench between the first and second source regions.

4. The semiconductor device according to claim 1, wherein the trench corners of each trench are rounded.

5. The semiconductor device according to claim 1, wherein the sidewall spacers have a width of about 10 Å

to about 2,000 Å

.

6. The semiconductor device according to claim 1, further comprising a metal silicide layer on the drain region.

7. The semiconductor device according to claim 6, further comprising:

a dielectric interlayer on the main surface;

a through-hole in the dielectric interlayer exposing a surface portion of the metal silicide layer on the drain region; and

a contact plug filling the through-hole in electrical contact wit h th e drain region.

8. The semiconductor device according to claim 1, wherein each tunnel dielectric layer comprises a nitrided silicon oxide.

9. The semiconductor device according to claim 1, wherein each dielectric layer comprises a composite of sequential layers of silicon oxide, silicon nitride and silicon oxide.

10. The semiconductor device according to claim 1, wherein each trench has a width of about 0.1 microns to about 0.5 microns and extends into the substrate to a depth of about 0.1 microns to about 0.5 microns.

11. The semiconductor device according to claim 1, wherein each tunnel dielectric layer has a thickness less than about 1,000 Å

.

12. The semiconductor device according to claim 1, wherein each floating gate electrode has a substantially uniform thickness of about 100 Å

to about 1,500 Å

.

13. The semiconductor device according to claim 1, wherein the second portion of each control gate electrode has a thickness of about 1,000 Å

to about 3,000 Å

.

14. A method of manufacturing a semiconductor device, which method comprises:

forming first and second trenches in a substrate, each trench comprising;

(a) first and second side surfaces intersecting the main surface at edges and extending into the substrate; and

(b) a bottom surface joining the first side surface at a first corner and the second side surface at a second corner within the substrate;

forming a substantially U-shaped tunnel dielectric layer lining each trench;

forming a substantially U-shaped floating gate electrode on the tunnel dielectric layer in each trench;

forming a dielectric layer on each floating gate electrode extending on the trench edges and a portion of the main surface terminating in side surfaces;

forming a control gate on each dielectric layer, each control gate comprising;

(a) a first portion extending below the main surface on the dielectric layer in each trench; and

(b) a second portion extending on each dielectric layer on the main surface terminating in side surfaces;

forming a drain region containing an impurity of a first conductivity type extending from the main surface into the substrate to a first depth between the second side surface of the first trench and the first side surface of the second trench;

forming a first source region extending from the main surface into the substrate to a second depth, greater than the first depth, along the first side surface of the first trench;

forming a second source region extending from the main surface into the substrate to a third depth, greater than the first depth, along the second side surface of the second trench; and

ion implanting to form an impurity region of the first conductivity type extending from the main surface at each trench edge into the substrate and entirely within a source/drain implant region;

wherein,

the semiconductor device comprises a channel region containing an impurity of a second conductivity type extending between the second side surface of the first trench and first side surface of the second trench under the drain region.

15. The method according to claim 14, wherein the second and third depths are substantially the same.

16. The method according to claim 15, wherein the first and second source regions and the channel region extends into the substrate to a depth less than the trench corners.

17. The method according to claim 16, comprising planarizing the main surface after forming each floating gate electrode and before forming each dielectric layer.

18. The method according to claim 15, comprising:

forming the first source region to extend into the substrate below the first side surface along the first corner and along the bottom surface of the first trench;

forming the second source region to extend into the substrate below the second side surface along the second corner and along the bottom surface of the second trench, and the channel region extends vertically along the trench sidewall.

19. The method according to claim 15, comprising thermally forming a sacrificial oxide liner in each trench and removing the sacrificial oxide liner from each trench prior to forming the tunnel dielectric layer in each trench, thereby rounding the trench corners.

20. The method according to claim 14, comprising:

ion implanting impurities of a second conductivity type at a dosage of about 5×

10¹⁴ atoms cm^-2 to about 1×

16 atoms cm^-2 and at an energy of about 1 KeV to about 30 KeV to form the drain implant region; and

implanting impurities of the second conductivity type at a dosage of about 5×

10¹⁴ atoms cm^-2 to about 1×

10¹⁶ atoms cm^-2 and at a dosage of about 10 KeV to about 500 KeV to form the first and second source implant regions.

21. The method according to claim 14, comprising ion implanting impurities of the first conductivity type to form the impurity region extending from the main surface at each trench edge into the substrate entirely within a source/drain region at an implant dosage of 1×

10¹³ atoms cm^-2 to about 1×

10¹⁵ atoms cm^-2 at an implantation energy of about 1 KeV to about 20 KeV.

22. A semiconductor device comprising:

a substrate having a main surface and containing an impurity of a first conductivity type;

first and second trenches formed in the substrate, each trench comprising;

(a) first and second side surfaces intersecting the main surface at edges and extending into the substrate; and

(b) a bottom surface joining the first side surface at a first corner and the second side surface at a second corner within the substrate;

a substantially U-shaped tunnel dielectric layer lining each trench;

a substantially U-shaped floating gate electrode on the tunnel dielectric layer in each trench;

a dielectric layer on each floating gate electrode and extending on the edges and a portion of the main surface terminating in side surfaces; and

a control gate electrode having;

(a) a first portion extending below the main surface on the dielectric layer in each trench; and

(b) a second portion extending on each dielectric layer on the main surface terminating in side surfaces;

a drain region containing an impurity of a second conductivity type extending from the main surface into the substrate to a first depth between the second side surface of the first trench and the first side surface of the second trench;

a channel region containing an impurity of the first conductivity type extending between the second side surface of the first trench and first side surface of the second trench deeper into the substrate than the drain region;

a first source region, containing an impurity of the second conductivity type, and extending from the main surface into the substrate to a second depth, greater than the first depth, along the first side surface of the first trench;

a second source region, containing an impurity of the second conductivity type, and extending from the main surface into the substrate to a third depth, greater than the first depth, along the second side surface of the second trench; and

an impurity region of the first conductivity type extending from the main surface at each trench edge of each trench into the substrate and entirely within a source/drain region.

23. The semiconductor device according to claim 22, wherein the first and second source regions extend into the substrate to a depth less than the trench corners.

24. The semiconductor device according to claim 22, wherein:

the first source region extends into the substrate below the first side surface along the first corner and along the bottom surface of the first trench;

the second source region extends into the substrate below the second side surface along the second corner and along the bottom surface of the second trench; and

the channel region extends below the second corner of the first trench and below the first corner of the second trench between the first and second source regions.

25. The semiconductor device according to claim 22, wherein the trench corners of each trench are rounded.

26. The semiconductor device according to claim 22, further comprising sidewall spacers on the side surfaces of the dielectric layers and second portion of the control gate electrodes.

27. The semiconductor device according to claim 22, further comprising a metal silicide layer on the drain region.

28. The semiconductor device according to claim 27, further comprising:

a dielectric interlayer on the main surface;

a through-hole in the dielectric interlayer exposing a surface portion of the metal silicide layer on the drain region; and

a contact plug filling the through-hole in electrical contact with the drain region.