Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
First Claim
1. An integrated circuit comprising:
- first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate, wherein the first and second gate conductors are interposed between respective first and second opposed sidewall surfaces;
first and second pairs of sidewall spacers extending laterally from the respective first and second opposed sidewall surfaces to respective first and second outer edges;
third and fourth pairs of sidewall spacers extending laterally from the first and second outer edges, respectively, to respective third and fourth outer edges;
a first pair of lightly doped drain areas residing within the first active area, wherein each of the first pair of lightly doped drain areas is formed aligned with one of said first opposed sidewall surfaces of said first gate conductor;
first source and drain regions arranged within the first active area laterally adjacent the first lightly doped drain areas, wherein the first source and drain regions are formed aligned at a point between the third outer edges and the first outer edges; and
a second pair of lightly doped drain areas residing within the second active area, wherein each of the second pair of lightly doped drain areas is formed aligned with the second outer edge of one of the second pair of sidewall spacers.
1 Assignment
0 Petitions
Accused Products
Abstract
A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n source/drain ("S/D") implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p- LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
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Citations
16 Claims
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1. An integrated circuit comprising:
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first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate, wherein the first and second gate conductors are interposed between respective first and second opposed sidewall surfaces; first and second pairs of sidewall spacers extending laterally from the respective first and second opposed sidewall surfaces to respective first and second outer edges; third and fourth pairs of sidewall spacers extending laterally from the first and second outer edges, respectively, to respective third and fourth outer edges; a first pair of lightly doped drain areas residing within the first active area, wherein each of the first pair of lightly doped drain areas is formed aligned with one of said first opposed sidewall surfaces of said first gate conductor; first source and drain regions arranged within the first active area laterally adjacent the first lightly doped drain areas, wherein the first source and drain regions are formed aligned at a point between the third outer edges and the first outer edges; and a second pair of lightly doped drain areas residing within the second active area, wherein each of the second pair of lightly doped drain areas is formed aligned with the second outer edge of one of the second pair of sidewall spacers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit, comprising:
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a first gate conductor laterally spaced from a second gate conductor, wherein said first and second gate conductors each have respective opposed sidewalls, wherein said first and second gate conductors are formed over a semiconductor substrate; first spacers having first outer edges;
wherein one of said first spacers is on each of said opposed sidewalls of said first and second gate conductors;second spacers having second outer edges, wherein one of said second spacers is on the first outer edge of each of said first spacers; first source and drain regions within said semiconductor substrate on opposite sides of said first gate conductor, wherein said first source and drain regions are formed aligned at a point between the first and the second outer edges of the first and second spacer respectively on the first gate conductor; and second source and drain regions within said semiconductor substrate on opposite sides of said second gate conductor, wherein said second source and drain regions are formed aligned with the second outer edges of the second spacers on the first outer edges of the first spacers on said second gate conductor. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An integrated circuit, comprising:
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a first transistor having a first gate conductor and first lightly doped regions formed within a semiconductor substrate and aligned to opposed sidewalls of the first gate conductor, the first transistor further including a first pair of spacers on the opposed sidewalls of the first gate conductor and first source and drain regions on opposite sides of the first gate conductor and aligned at a point laterally spaced from said outer edges of said first pair of spacers; and a second transistor having a second gate conductor and a second pair of spacers on opposed sidewalls of said second gate conductor, the second transistor further including second lightly doped regions formed within the semiconductor substrate and aligned to outer edges of said second pair of spacers, the second transistor further including a third pair spacers on the outer edges of the second pair of spacers and second source and drain regions formed within the semiconductor substrate aligned to outer edges of the third pair of spacers; wherein said first source and drain regions are laterally closer to the sidewalls of said first gate conductor than said second source and drain regions are to the sidewalls of said second gate conductor. - View Dependent Claims (15, 16)
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Specification