Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

• US 6,124,610 A
• Filed: 06/26/1998
• Issued: 09/26/2000
• Est. Priority Date: 06/26/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheek, Jon D., Wristers, Derick J., Toprac, Anthony J.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/105,872
• Time in Patent Office: 823 Days
• Field of Search: 257/344, 257/336, 257/328, 438/184, 438/185
• US Class Current: 257/328
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n source/drain ("S/D") implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p^- LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.

Claims

1. An integrated circuit comprising:

first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate, wherein the first and second gate conductors are interposed between respective first and second opposed sidewall surfaces;

first and second pairs of sidewall spacers extending laterally from the respective first and second opposed sidewall surfaces to respective first and second outer edges;

third and fourth pairs of sidewall spacers extending laterally from the first and second outer edges, respectively, to respective third and fourth outer edges;

a first pair of lightly doped drain areas residing within the first active area, wherein each of the first pair of lightly doped drain areas is formed aligned with one of said first opposed sidewall surfaces of said first gate conductor;

first source and drain regions arranged within the first active area laterally adjacent the first lightly doped drain areas, wherein the first source and drain regions are formed aligned at a point between the third outer edges and the first outer edges; and

a second pair of lightly doped drain areas residing within the second active area, wherein each of the second pair of lightly doped drain areas is formed aligned with the second outer edge of one of the second pair of sidewall spacers.

2. The integrated circuit of claim 1, wherein the first pair of lightly doped drain areas comprise a first concentration of n-type dopant species.

3. The integrated circuit of claim 1, wherein the second pair of lightly dope drain areas comprise a first concentration of p-type dopant species.

4. The integrated circuit of claim 3, wherein the first active area and the second active area are laterally spaced apart by an isolation structure.

5. The integrated circuit of claim 4, wherein said first source and drain regions have a second concentration of n-type dopant species greater than the first concentration of n-type dopant species.

6. The integrated circuit of claim 5, further comprising second source and drain regions arranged within the second active area laterally adjacent the second lightly doped drain areas and having a second concentration of p-type dopant species greater than the first concentration of p-type dopant species, wherein the second source and drain regions are formed aligned with the fourth outer edges of the fourth pair of sidewall spacers.

7. The integrated circuit of claim 1, wherein said first and second pairs of sidewall spacers have a first lateral width that is approximately the same for both said first and second pairs, and wherein said third and fourth pairs of sidewall spacers have a second lateral width that is approximately the same for both said third and fourth pairs.

8. An integrated circuit, comprising:

a first gate conductor laterally spaced from a second gate conductor, wherein said first and second gate conductors each have respective opposed sidewalls, wherein said first and second gate conductors are formed over a semiconductor substrate;

first spacers having first outer edges;

wherein one of said first spacers is on each of said opposed sidewalls of said first and second gate conductors;

second spacers having second outer edges, wherein one of said second spacers is on the first outer edge of each of said first spacers;

first source and drain regions within said semiconductor substrate on opposite sides of said first gate conductor, wherein said first source and drain regions are formed aligned at a point between the first and the second outer edges of the first and second spacer respectively on the first gate conductor; and

second source and drain regions within said semiconductor substrate on opposite sides of said second gate conductor, wherein said second source and drain regions are formed aligned with the second outer edges of the second spacers on the first outer edges of the first spacers on said second gate conductor.

9. The integrated circuit as recited in claim 8, further comprising lightly doped regions within said semiconductor substrate, wherein said lightly doped regions are formed on opposite sides of said first gate conductor aligned with the opposed sidewalls of said first gate conductor.

10. The integrated circuit as recited in claim 8, further comprising lightly doped regions within said semiconductor substrate, wherein said lightly doped regions are formed on opposite sides of said second gate conductor aligned with the first outer edges of the first spacers on the opposed sidewalls of the second gate conductor.

11. The integrated circuit as recited in claim 8, wherein said first source and drain regions comprise n-type dopants and said second source and drain regions comprise p-type dopants.

12. The integrated circuit as recited in claim 8, wherein said first spacers all have approximately the same lateral width.

13. The integrated circuit as recited in claim 8, wherein said second spacers all have approximately the same lateral width.

14. An integrated circuit, comprising:

a first transistor having a first gate conductor and first lightly doped regions formed within a semiconductor substrate and aligned to opposed sidewalls of the first gate conductor, the first transistor further including a first pair of spacers on the opposed sidewalls of the first gate conductor and first source and drain regions on opposite sides of the first gate conductor and aligned at a point laterally spaced from said outer edges of said first pair of spacers; and

a second transistor having a second gate conductor and a second pair of spacers on opposed sidewalls of said second gate conductor, the second transistor further including second lightly doped regions formed within the semiconductor substrate and aligned to outer edges of said second pair of spacers, the second transistor further including a third pair spacers on the outer edges of the second pair of spacers and second source and drain regions formed within the semiconductor substrate aligned to outer edges of the third pair of spacers;

wherein said first source and drain regions are laterally closer to the sidewalls of said first gate conductor than said second source and drain regions are to the sidewalls of said second gate conductor.

15. The integrated circuit as recited in claim 14, wherein said first transistor is an NMOS transistor and said second transistor is a PMOS transistor.

16. The integrated circuit as recited in claim 14, wherein said first pair of spacers and said second pair of spacers all have approximately the same lateral width.