FET with source-substrate connection and method for producing the FET

• US 6,124,612 A
• Filed: 09/13/1999
• Issued: 09/26/2000
• Est. Priority Date: 01/15/1998
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Werner, Wolfgang, Tihanyi, Jenoe
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/395,302
• Time in Patent Office: 379 Days
• Field of Search: 257/327, 257/329, 257/330, 257/331, 257/332, 257/712, 257/713, 257/720
• US Class Current: 257/330
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An FET with a source-substrate connection (source-down FET) and a trench gate includes a drain zone of a first conductivity type provided on a first surface of a semiconductor layer of the first conductivity type that is disposed on a semiconductor substrate of the first conductivity type. The trench gate substantially penetrates the semiconductor layer. A source zone of the first conductivity type is provided at an end of the trench on a second surface of the semiconductor layer. A semiconductor zone of the second conductivity type is provided in a region next to the trench on the second surface of the semiconductor layer. The semiconductor zone has a surface which forms the second surface of the semiconductor layer together with the surface of the source zone. A method for producing the FET is also provided.

Claims

1. An FET with a source-substrate connection and a trench gate, comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer of the first conductivity type disposed on said semiconductor substrate, said semiconductor layer having first and second surfaces;

a drain zone of the first conductivity type disposed on said first surface of said semiconductor layer;

a trench gate substantially penetrating said semiconductor layer, said trench gate having an end and defining a region next to said trench gate on said second surface of said semiconductor layer;

a source zone of the first conductivity type disposed at said end of said trench gate on said second surface of said semiconductor layer, said source zone having a surface;

a semiconductor zone of the second conductivity type disposed in said region next to said trench gate on said second surface of said semiconductor layer, said semiconductor zone having a surface forming said second surface of said semiconductor layer together with said surface of said source zone; and

a buried highly conductive layer disposed between said second surface of said semiconductor layer and said semiconductor substrate.

2. The FET according to claim 1, wherein said highly conductive layer is formed of a material forming an ohmic contact with said source zone and said semiconductor zone of the second conductivity type.

3. The FET according to claim 2, wherein said material is selected from the group consisting of silicide, titanium nitride and a similar material.

4. The FET according to claim 1, wherein said highly conductive layer is formed of polycrystalline silicon doped with a dopant of the first conductivity type.

5. The FET according to claim 4, wherein said semiconductor zone of the second conductivity type is doped high enough to create a pn junction extending within said polycrystalline highly conductive layer.

6. The FET according to claim 1, wherein said semiconductor substrate is formed of highly conductive silicon.

7. The FET according to claim 1, wherein said semiconductor substrate is formed of a plurality of silicon layers.

8. The FET according to claim 1, including a wafer bonding surface extending between said semiconductor substrate and said highly conductive layer.

9. The FET according to claim 1, including a wafer bonding surface extending between said semiconductor layer and said highly conductive layer.

10. The FET according to claim 1, wherein said semiconductor substrate has a layer thickness of from 5 to 10 μ

m.

11. The FET according to claim 1, wherein said drain zone has a thickness or penetration depth below 1 μ

m.

12. The FET according to claim 1, wherein said highly conductive layer has a layer thickness of approximately 0.01 μ

m.

13. The FET according to claim 1, wherein said semiconductor substrate has a layer thickness of from 50 to 200 μ

m.

14. The FET according to claim 1, wherein said semiconductor zone of the second conductivity type has a layer thickness of from 2 to 5 μ

m.

15. The FET according to claim 1, wherein said source zone has a thickness or penetration depth of from 1 to 3 μ

m.

16. The FET according to claim 1, including a drain metallizing having a layer thickness of from 1 to 5 μ

m.

17. The FET according to claim 1, including a drain metallizing having a layer thickness of 3 μ

m.

18. The FET according to claim 1, wherein said trench gate is one of a plurality of adjacent trench gates having a mutual spacing of approximately 5 μ

m.

19. The FET according to claim 1, including a region adjoining said highly conductive layer, said semiconductor zone of the second conductivity type being highly doped in said region.

20. The FET according to claim 1, including a plurality of gates connected in parallel and a grounded edge gate.

21. The FET according to claim 1, wherein said trench gate is one of a plurality of adjacent trench gates, an insulating layer is disposed on said semiconductor layer, and polycrystalline silicon fillings in said trench gates have hat-like lateral extensions in the vicinity of said insulating layer.

22. The FET according to claim 1, wherein said semiconductor substrate is formed of a material selected from the group consisting of monocrystalline silicon and polycrystalline silicon.

23. A method for producing the FET according to claim 1, which comprises:

wafer-bonding said semiconductor wafer provided with said highly conductive layer to said semiconductor substrate.

24. A method for producing the FET according to claim 1, which comprises:

wafer-bonding said semiconductor substrate provided with said highly conductive layer to said semiconductor layer.

25. The method according to claim 23, which comprises mounting a pyramid-like polycrystalline silicon structure on said semiconductor substrate before the wafer bonding step, to provide exposed peaks of said pyramid-like structure to be utilized as adjustment markings after said semiconductor substrate has been ground thin.

26. The method according to claim 24, which comprises mounting a pyramid-like polycrystalline silicon structure on said semiconductor substrate before the wafer bonding step, to provide exposed peaks of said pyramid-like structure to be utilized as adjustment markings after said semiconductor substrate has been ground thin.