Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
First Claim
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1. A lateral MOSFET comprising:
- a barrier layer of a raised source/drain region located over a substrate and comprising a first material;
an upper layer of said raised source/drain region located over said barrier layer and comprising a second material different from said first material;
a gate dielectric located adjacent the raised source/drain region and located over a channel region of said substrate, said first material providing an energy band barrier between said raised source/drain region and said channel region; and
a gate electrode located over said gate dielectric;
wherein said gate electrode and gate dielectric are adjacent to a portion of said raised source/drain region, wherein said gate dielectric separates said gate electrode from said raised source/drain region.
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Abstract
A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).
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Citations
4 Claims
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1. A lateral MOSFET comprising:
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a barrier layer of a raised source/drain region located over a substrate and comprising a first material; an upper layer of said raised source/drain region located over said barrier layer and comprising a second material different from said first material; a gate dielectric located adjacent the raised source/drain region and located over a channel region of said substrate, said first material providing an energy band barrier between said raised source/drain region and said channel region; and a gate electrode located over said gate dielectric;
wherein said gate electrode and gate dielectric are adjacent to a portion of said raised source/drain region, wherein said gate dielectric separates said gate electrode from said raised source/drain region. - View Dependent Claims (2, 3, 4)
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Specification