Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region

• US 6,124,627 A
• Filed: 06/17/1999
• Issued: 09/26/2000
• Est. Priority Date: 12/03/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rodder, Mark S., Liu, William U.
• Primary Examiner(s): Hardy, David
• Application Number:
  US09/334,991
• Time in Patent Office: 467 Days
• Field of Search: 257/616, 257/77, 257/751, 438/300
• US Class Current: 257/616
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).

Claims

1. A lateral MOSFET comprising:

a barrier layer of a raised source/drain region located over a substrate and comprising a first material;

an upper layer of said raised source/drain region located over said barrier layer and comprising a second material different from said first material;

a gate dielectric located adjacent the raised source/drain region and located over a channel region of said substrate, said first material providing an energy band barrier between said raised source/drain region and said channel region; and

a gate electrode located over said gate dielectric;

wherein said gate electrode and gate dielectric are adjacent to a portion of said raised source/drain region, wherein said gate dielectric separates said gate electrode from said raised source/drain region.

2. The MOSFET of claim 1, wherein said upper layer comprises silicon and said barrier layer comprises silicon-carbide.

3. The MOSFET of claim 1, wherein said upper layer comprises silicon and said barrier layer comprises silicon-germanium.

4. The MOSFET of claim 1, wherein said first material provides an energy band barrier between said upper layer and said channel region.