Apparatus and method for testing semiconductor devices formed on a semiconductor wafer

• US 6,124,725 A
• Filed: 11/25/1998
• Issued: 09/26/2000
• Est. Priority Date: 11/29/1997
• Status: Expired due to Fees

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Sato, Takashi
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US09/199,782
• Time in Patent Office: 671 Days
• Field of Search: 324/765, 324/754, 324/758, 324/767, 324/756
• US Class Current: 324/754.03
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801

Abstract

The present specification and drawings disclose a testing apparatus designed for testing semiconductor elements formed on a semiconductor wafer. The testing apparatus comprises a main chuck having a surface on which a semiconductor wafer is placed, a contactor which is brought into contact with the semiconductor wafer, the contactor having probe terminals which are simultaneously brought into electric contact with a plurality of semiconductor elements formed on the semiconductor wafer, a reliability test mechanism for testing reliability of the semiconductor elements, an electric characteristic test mechanism for testing electric characteristics of the semiconductor element, and a switch mechanism for switching between the reliability test mechanism and the electric characteristic test mechanism such that the reliability test mechanism and the electric characteristic test mechanism are sequentially connected to the contactor when this contactor is in contact with the semiconductor wafer placed on the main chuck.

Claims

1. A testing apparatus for testing semiconductor devices formed on a semiconductor wafer, comprising:

a main chuck having a surface on which a semiconductor wafer is placed;

a contactor which is brought into contact with the semiconductor wafer, said contactor having probe terminals which are simultaneously brought into electric contact with a plurality of semiconductor devices formed on the semiconductor wafer;

a reliability test mechanism configured to test reliability of the semiconductor devices;

an electric characteristic configured to test electric characteristics of the semiconductor devices; and

a switch mechanism configured to switch between the reliability test mechanism and the electric characteristic test mechanism such that the reliability test mechanism and the electric characteristic test mechanism are sequentially connected to the contactor when the contactor is in contact with the semiconductor wafer placed on the main chuck.

2. A testing apparatus according to claim 1, wherein said main chuck includes a vacuum absorption mechanism for causing the semiconductor wafer to be absorbed on the surface of the main chuck, and at least one of the main chuck and the contactor includes gas supply means for supplying an inert gas into a gap which is formed between the contactor and the semiconductor wafer when the contactor and the semiconductor wafer are in contact with each other.

3. A testing apparatus according to claim 2, wherein one of said main chuck and said contactor includes a seal member for sealing a gap which is formed between the contactor and the semiconductor wafer when the contactor and the semiconductor wafer are in contact with each other.

4. A testing apparatus according to claim 1, wherein said contactor includes a temperature sensor for measuring a temperature of the semiconductor wafer.

5. A testing apparatus according to claim 1, further comprising:

an oxide film removing mechanism configured to remove an oxide film from surfaces of electrodes of the semiconductor devices formed on the semiconductor wafer.

6. A testing apparatus according to claim 5, wherein said oxide film removing mechanism is a plasma processing apparatus.

7. A testing method for testing semiconductor devices formed on a semiconductor wafer, comprising the steps of:

placing a semiconductor wafer on a main chuck;

bringing a contactor into contact with the semiconductor wafer, said contactor having probe terminals which are simultaneously brought into electric contact with electrodes of a plurality of semiconductor devices formed on the semiconductor wafer;

executing a reliability test by use of the contactor which is in contact with the semiconductor wafer; and

executing an electric characteristic test by use of the contactor which is in contact with the semiconductor wafer.

8. A testing method according to claim 7, wherein the step of placing the semiconductor wafer on the main chuck is preceded by a step of removing an oxide film from the surfaces of the electrodes of the semiconductor devices formed on the semiconductor wafer.

9. A testing method according to claim 7, wherein the step of placing the semiconductor wafer on the main chuck is preceded by a step of subjecting the semiconductor wafer to plasma processing, to thereby remove an oxide film from the surfaces of the electrodes of the semiconductor devices formed on the semiconductor wafer.

10. A test method according to claim 7, wherein at least one of the reliability test and the electric characteristic test is executed, with an inert gas kept supplied to a gap between the contactor and the semiconductor wafer.