Bias compensator for differential transmission line with voltage bias

• US 6,124,727 A
• Filed: 07/10/1998
• Issued: 09/26/2000
• Est. Priority Date: 07/11/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gintz, William C., Bridgewater, Jr., Walter Francis
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/113,729
• Time in Patent Office: 809 Days
• Field of Search: 326/33, 326/30, 326/56-58, 326/83, 326/86, 326/29, 326/87, 327/307, 327/362
• US Class Current: 326/33
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling

Abstract

A bias compensator circuit for significantly reducing an offset produced by a termination bias that is associated with a differential pair bus. The differential pair bus is connected to a driver. The bias compensator circuit includes: (a) a signal source connected to a first line of the differential pair; (b) a first switch for switching ON the signal source while the driver is driving; (c) a signal sink connected to a second line of the differential pair; and (d) a second switch for switching ON the signal sink while the driver is driving.

Claims

1. A bias compensator circuit for significantly reducing an offset produced by a termination bias that is associated with a differential pair bus connected to a driver, the bias compensator circuit comprising:

a signal source connected to a first line of the differential pair;

a first switch for switching ON the signal source while the driver is driving;

a signal sink connected to a second line of the differential pair; and

a second switch for switching ON the signal sink while the driver is driving, such that when the signal source and signal sink are ON, substantially all of the offset is cancelled.

2. A bias compensator circuit as recited in claim 1, wherein the first switch is a first tri-state detector that is configured to receive a tri-state drive signal while the driver is not driving, and the second switch is a second tri-state detector that is also configured to receive the tri-state drive signal when the driver is not driving.

3. A bias compensator circuit as recited in claim 1, wherein the signal source is connected to power and the signal sink is connected to ground when the driver is driving.

4. A bias compensator circuit as recited in claim 3, wherein when the signal source is connected to power and the signal sink is connected to ground, the offset is substantially reduced.

5. The bias compensator as recited in claim 1, wherein the termination bias is a voltage bias that is provided by a termination resistance of the bus, wherein the signal source is a current source, and wherein the signal source has a particular value that is substantially equal to the DC offset divided by one-half of the termination resistance.

6. The bias compensator as recited in claim 5, wherein an impedance of the current source is at least between about 5 times and about 6 times greater than an impedance of the bus when the bus is loaded.

7. The bias compensator as recited in claim 1, wherein the signal source is a voltage source.

8. The bias compensator as recited in claim 2, wherein the bias compensator is configured for placement substantially anywhere on the bus.

9. A differential bus system for facilitating communication between computer devices, the differential bus system comprising:

a bus including a termination bias that produces an offset;

a symmetrical driver connected to the bus; and

a bias compensator that is capable of significantly reducing the offset, wherein the bias compensator is integrated with the symmetrical driver, and the bias compensator is configured to turn on when the symmetrical driver is driving, and to turn off when the symmetrical driver is in a condition that is different than driving;

wherein the bus is capable of decoding bus phases and of supplying a command to switch on the bias compensator without requiring an additional separate line on the bus.

10. The differential bus system as recited in claim 9, further comprising at least one additional symmetrical driver connected to the bus and connected to the bias compensator.

11. The differential bus system as recited in claim 10, wherein the bus has a point-to-point configuration.

12. The differential bus system as recited in claim 10, wherein the bus has a bi-directional half-duplex configuration and a multi-drop configuration.

13. The differential bus system as recited in claim 9, wherein the offset is a DC offset.

14. The differential bus system as recited in claim 9, further comprising at least one asymmetrical driver connected to the bus.

15. The differential bus system as recited in claim 9, further comprising:

at least one additional symmetrical driver connected to the bus; and

at least one additional bias compensator integrated with the at least one additional symmetrical driver.

16. The differential bus system as recited in claim 9, wherein the termination bias is a voltage bias, and wherein the bias compensator is a voltage bias compensator.

17. The differential bus system as recited in claim 9, wherein the termination bias is previously unknown and wherein the bias compensator is capable of automatically supplying increasing signal until the termination bias is cancelled, and is capable of then automatically stopping the signal increase.

18. A method for significantly reducing an offset produced by a termination bias that is associated with a differential pair bus connected to a driver, the method comprising:

providing a first switch and a second switch for detecting whether the driver is driving the bus;

electrically connecting a signal source to one of the differential pair, for providing a current from a power line to the one of the differential pair when the switch detects whether the driver is driving the bus; and

electrically connecting a signal sink to another of the differential pair, for providing a current from the another of the differential pair to ground when the switch detects whether the driver is driving the bus.

19. The method as recited in claim 18, further comprising:

integrating the first switch, second switch, signal source, and signal sink to be a part of the driver.

20. The method as recited in claim 19, wherein providing the first switch and second switch includes providing a first transistor and a second transistor, respectively, that are each configured to be turned on when the driver is driving;

wherein electrically connecting a signal source to one of the differential pair includes connecting a resistor between the power line and the first transistor; and

wherein electrically connecting a signal sink to another of the differential pair includes connecting a resistor between the second transistor and ground.

21. A differential bus system for facilitating communication between computer devices, the differential bus system comprising:

a bus including a termination bias that produces an offset;

a symmetrical driver connected to the bus; and

a bias compensator that is capable of significantly reducing the offset, the bias compensator including,

a signal source connected to a first line of a differential pair of the bus;

a signal sink connected to a second line of the differential pair;

a first switch connected to the signal source and configured to turn the signal source ON when the symmetrical driver is driving; and

a second switch connected to the signal sink and configured to turn the signal sink ON when the symmetrical driver is driving.

22. The differential bus system as recited in claim 21, wherein the first switch is a first tri-state detector, and the second switch is a second tri-state detector.

23. The differential bus system as recited in claim 21, wherein the first switch includes at least one transistor, and wherein the second switch includes at least one transistor.

24. The differential bus system as recited in claim 23, wherein the signal source includes a first resistor and is connected to a voltage power source, and wherein the signal sink includes a second resistor and is connected to ground.

25. The differential bus system as recited in claim 24, wherein the signal source further includes a first inductive component that is connected to the first resistor, and the signal sink further includes a second inductive component that is connected to the second resistor.

26. The differential bus system as recited in claim 21, wherein the signal source includes a first reactive source impedance, and wherein the signal sink includes a second reactive source impedance, each of which are capable of compensating for a capacitive load on the bus.

27. The differential bus system as recited in claim 21, wherein the signal source includes at least one transistor, and wherein the signal sink includes at least one transistor.