Input buffer providing virtual hysteresis

• US 6,124,733 A
• Filed: 12/22/1997
• Issued: 09/26/2000
• Est. Priority Date: 12/22/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sharpe-Geisler, Bradley A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US08/996,442
• Time in Patent Office: 1,009 Days
• Field of Search: 326/31, 326/33, 326/34, 326/83, 326/87, 326/86, 326/24, 327/108, 327/112, 327/262, 327/205, 327/206
• US Class Current: 326/83
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414). After a low to high buffer input transition above a level (H1), the inverter (420) will transition and the NMOS transistors (404 and 414) will turn on together to create a path to Vss with transistor (604) of inverter (400) to decrease the buffer threshold to (H2). After the buffer input rises further above a threshold (H1A) of inverter (431) combined with inverter (440), inverter (433) will turn off transistor (414) to set the buffer threshold back to (H1). After a high to low buffer input transition below a level (H1), the inverter (420) will transition and the PMOS transistors (402 and 412) will both be on together to create a path to Vdd with transistor (602) of inverter (400) to increase the buffer threshold to (H3). After the buffer input falls further below a threshold (H1B) of inverters (431) and (440), inverter (433) will turn off transistor (412) to set the buffer threshold back to (H1).

Claims

1. A buffer comprising:

a first inverter having an input providing the buffer input and an output providing the buffer output, the first inverter comprising;

a first PMOS transistor having a source to drain path coupling Vdd to the buffer output and a gate coupled to the buffer input; and

a first NMOS transistor having a source to drain path coupling the buffer output to Vss and a gate coupled to the buffer input;

a second PMOS transistor;

a second NMOS transistor; and

a threshold altering means coupled to the buffer input, the buffer output and to the second PMOS and NMOS transistors, the threshold altering means enabling the source to drain path of the second NMOS transistor to provide Vss to the buffer output for a first time period after the buffer input transitions from low to high, the first time period beginning after the buffer output transitions in response to the low to high buffer input transition and potentially ending before the input transitions from high back to low, the threshold altering means preventing the source to drain path of the second NMOS transistor from providing Vss to the buffer output before and after the first time period, the threshold altering means further enabling the source to drain path of the second PMOS transistor to provide Vdd to the buffer output for a second time period after the buffer input transitions from high to low, the second time period beginning after the buffer output transitions in response to the high to low buffer input transition and potentially ending before the buffer input transitions from low back to high, the threshold altering means preventing the source to drain path of the second PMOS transistor from providing Vdd to the buffer output before and after the second time period.

2. The buffer of claim 1,

wherein a threshold of the first inverter has a first value (H1), and

wherein the first time period is a time required for the buffer input to transition substantially from (H1) to a value (H1A) which is between (H1) and a value for high, and

wherein the second time period is a time required for the buffer input to transition substantially from (H1) to a value (H1B) which is between (H1) and a value for low.

3. The buffer of claim 2, wherein the threshold altering means comprises:

a third PMOS transistor having a source to drain path coupling the source to drain path of the second PMOS transistor to Vdd, and having a gate;

a third NMOS transistor having a source to drain path coupling the source to drain path of the second NMOS transistor to Vss, and having a gate;

a second inverter coupling the output of the first inverter to a gate of the second PMOS transistor and to a gate of the second NMOS transistor;

a third inverter having an input coupled to the buffer input, and having an output;

a latch having a first terminal coupled to the output of the third inverter and having a second terminal; and

a fourth inverter having an input coupled to the second terminal of the latch, and having an output coupled to the gate of the third PMOS transistor and to the gate of the third NMOS transistor.

4. The buffer of claim 3, wherein the latch comprises:

a fifth inverter having an input forming the first terminal of the latch and an output forming the second terminal of the latch; and

a sixth inverter having an input coupled to the output of the fifth inverter, and an output coupled to the input of the fifth inverter.

5. The buffer of claim 1, wherein the threshold altering means comprises:

a third PMOS transistor having a source to drain path coupling the source to drain path of the second PMOS transistor to Vdd, and having a gate;

a third NMOS transistor having a source to drain path coupling the source to drain path of the second NMOS transistor to Vss, and having a gate;

a second inverter coupling the output of the first inverter to a gate of the second PMOS transistor and to a gate of the second NMOS transistor, and

three series inverters coupling the buffer input to a gate of the third PMOS transistor and to the gate of the third NMOS transistor.

6. The buffer of claim 5,

wherein the first time period and second time period are substantially a difference between the delay through the first and second inverters and a delay through the three series inverters.

7. The buffer of claim 1, wherein the threshold altering means comprises:

a third PMOS transistor having a source to drain path coupling the source to drain path of the second PMOS transistor to Vdd, and having a gate;

a third NMOS transistor having a source to drain path coupling the source to drain path of the second NMOS transistor to Vss, and having a gate;

a second inverter coupling the output of the first inverter to a gate of the second PMOS transistor and to a gate of the second NMOS transistor;

a Schmitt trigger coupling the buffer input to the gate of the third PMOS transistor and to the gate of the third NMOS transistor.

8. The buffer of claim 1, wherein gates of the second NMOS transistor and the second PMOS transistor are coupled to the buffer input, and wherein the threshold altering means comprises:

a third PMOS transistor having a source to drain path coupling the source to drain path of the second PMOS transistor to Vdd, and having a gate;

a third NMOS transistor having a source to drain path coupling the source to drain path of the second NMOS transistor to Vss, and having a gate; and

a Schmitt trigger coupling the buffer input to the gate of the third PMOS transistor and to the gate of the third NMOS transistor.

9. A buffer comprising:

a first CMOS inverter having an input providing the buffer input and an output providing the buffer output;

a first PMOS transistor having a source coupled to Vdd, a drain and a gate;

a second PMOS transistor having a source coupled to the drain of the first PMOS transistor, a drain coupled to the buffer output, and having a gate;

a first NMOS transistor having a drain coupled to the buffer output, a source and a gate;

a second NMOS transistor having a drain coupled to the source of the first NMOS transistor, a source coupled to Vss, and having a gate;

a second inverter coupling the output of the first inverter to the gate of the first PMOS transistor and to the gate of the first NMOS transistor, and third, fourth, and fifth series inverters coupling the buffer input to the gate of the second PMOS transistor and to the gate of the second NMOS transistor.

10. The buffer of claim 9 further comprising:

a sixth inverter having an input coupled to an output of the fourth inverter, and an output coupled to an input of the fourth inverter.

11. A buffer comprising:

a first CMOS inverter having an input providing the buffer input and an output providing the buffer output;

a first PMOS transistor having a source coupled to Vdd, gate coupled to the buffer input, and having a drain;

a second PMOS transistor having a source coupled to the drain of the first PMOS transistor, a drain coupled to the buffer output, and having a gate;

a first NMOS transistor having a drain coupled to the buffer output, a gate coupled to the buffer input, and having a source;

a second NMOS transistor having a drain coupled to the source of the first NMOS transistor, a source coupled to Vss, and having a gate;

a Schmitt trigger coupling the buffer input to the gates of the second PMOS transistor and the second NMOS transistor.

12. The buffer of claim 11, wherein the gates of the first PMOS transistor and the first NMOS transistor are coupled to the buffer input through the first CMOS inverter and a second inverter connected in series.