Reference voltage generation circuit for comparator

• US 6,124,743 A
• Filed: 01/25/1999
• Issued: 09/26/2000
• Est. Priority Date: 08/24/1996
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Yang, Yil-Suk
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/235,748
• Time in Patent Office: 610 Days
• Field of Search: 327/540, 327/77, 327/78, 327/89, 327/88, 327/87, 327/91, 327/94, 327/95, 327/96, 327/124, 327/164, 327/130, 327/131, 323/314
• US Class Current: 327/198
• CPC Class Codes: H03K 5/082 with an adaptive threshold

Abstract

A reference voltage generation circuit which is capable of generating a reference voltage having multiple steps by using a periodic response characteristic of a chaotic circuit. The circuit includes a first sample/hold unit for sampling and holding a periodic output voltage V3 in accordance with a first clock signal CLK1 from an externally connected clock signal generation unit, a second sample/hold unit for sampling and holding an output voltage V3'"'"' from the first sample/hold unit in accordance with a second clock signal CLK2 from the externally connected clock signal generation unit, a non-linear unit for receiving voltage V4 from the second sample/hold unit and outputting a non-linear voltage V2 signal having a sawtooth-shaped transfer characteristic, and an addition unit for adding the non-linear voltage signal V2 from the non-linear unit and an externally applied voltage signal V1 and outputting the periodic output voltage V3.

Claims

1. A reference voltage generation circuit for a comparator having an operational amplifier connected between a power supply voltage and a ground voltage, an inverting terminal of the operational amplifier receives an input voltage and a non-inverting terminal of which receives a reference voltage, comprising:

a first sample/hold unit for sampling and holding a periodic output voltage in accordance with a first clock signal;

a second sample/hold unit for sampling and holding an output voltage from said first sample/hold unit in accordance with a second clock signal;

a non-linear unit for outputting a non-linear voltage having a sawtooth-shaped transfer characteristic in accordance with an output voltage from said second sample/hold unit; and

an addition unit for adding the non-linear voltage signal from said non-linear unit and an externally applied voltage and outputting the periodic output voltage to said first sample/hold unit and as the reference voltage to the operational amplifier of the comparator.

2. The circuit of claim 1, wherein each of said first and second sample/hold units comprises:

an inverter for inverting one of the clock signals;

a transmission gate for transmitting the output voltage to an output terminal when the clock signal is a high level, an inverting control terminal of said transmission gate receives an output signal from said inverter, and a non-inverting control terminal of which receives the clock signal; and

a capacitor coupled to the output terminal for receiving an output signal from said transmission gate.

3. The circuit of claim 1, wherein said non-linear unit comprises:

a first variable resistor for receiving an input signal;

an operational amplifier connected between a power supply voltage and a negative power supply voltage, an inverting input terminal of said operational amplifier is connected in series with said first variable resistor, a non-inverting input terminal of said operational amplifier is connected with ground, and an output terminal of which is connected in series with a second variable resistor;

a third variable resistor connected such that an output signal from the second variable resistor is fed back to said first variable resistor; and

a fourth variable resistor connected such that the output signal from the second variable resistor is fed back to the inverting input terminal of said operational amplifier.

4. The circuit of claim 1, wherein said addition unit comprises:

a first resistor having first and second electrodes;

a second resistor having first and second electrodes;

a third resistor having first and second electrodes; and

an operational amplifier having first and second input electrodes and an output electrode;

wherein the first electrode of said first resistor receives the externally applied voltage and the first electrode of said second resistor receives the non-linear voltage, the second electrodes of said first, second and third resistors are coupled to the first input electrode of said operational amplifier and the second input electrode is coupled to a prescribed potential, and the first electrode of said third resistor is coupled to the output electrode of said operational amplifier.

5. A reference voltage generating circuit, comprising:

a signal generating unit responsive to an input voltage to generate a non-linear signal, said signal generating unit combining the non-linear signal with an externally applied voltage to provide a reference voltage; and

a sample and hold circuit coupled to said signal generating unit for receiving the reference voltage, said sample and hold circuit responsive to two different clock signals, which do not overlap with each other, for providing the input voltage to said signal generating unit.

6. The circuit of claim 5, wherein said signal generating unit comprises:

a non-linear unit with a sawtooth transfer characteristic for receiving the input voltage and generating the non-linear signal; and

an addition unit for combining the non-linear signal with the externally applied voltage signal to provide the reference voltage.

7. The circuit of claim 6, wherein said non-linear unit comprises:

a first resistor having first and second electrodes;

a second resistor having first and second electrodes;

a third resistor having first and second electrodes;

a fourth resistor having first and second electrodes; and

a first operational amplifier having first and second input electrodes and an output electrode, wherein the first electrode of said first and third resistors are coupled to receive the input voltage, the second electrode of said first resistor and the first electrode of said fourth resistor are coupled to the first input electrode of said first operational amplifier and the second input electrode is coupled to a first prescribed potential, and the first electrode of said second resistor is coupled to the output electrode of said first operational amplifier, and the second electrode of said third and fourth resistors are coupled to the second electrode of said second resistor.

8. The circuit of claim 7, wherein said addition unit comprises:

a fifth resistor having first and second electrodes;

a sixth resistor having first and second electrodes;

a seventh resistor having first and second electrodes; and

a second operational amplifier having first and second input electrodes and an output electrode, wherein the first electrode of said fifth resistor receives the externally applied voltage and the first electrode of said sixth resistor receives the non-linear signal, the second electrodes of said fifth, sixth, and seventh resistors are coupled to the first input electrode of said second operational amplifier and the second input electrode is coupled to a second prescribed potential, and the first electrode of said seventh resistor is coupled to the output electrode of said second operational amplifier.

9. The circuit of claim 8, wherein said sample and hold circuit comprises:

a first sample and hold circuit coupled to the output of said addition unit for receiving the reference voltage and coupled for receiving a first clock signal; and

a second sample and hold unit coupled for receiving an output from said first sample and hold circuit, coupled for receiving a second clock signal, and coupled to said non-linear unit, wherein said first and second clock signals do not overlap, and wherein the output of said second sample and hold provides the input voltage to said non-linear unit.

10. The circuit of claim 9, wherein said first sample and hold circuit comprises:

a first inverter having an input electrode and an output electrode;

a first capacitor having an input electrode and an output electrode; and

a first transmission gate having an input electrode, an output electrode, and first and second control electrodes, wherein the input electrode of said first inverter and the first control electrode of said first transmission gate are coupled for receiving the first clock signal, the output electrode of said first inverter is coupled to the second control electrode of said first transmission gate, the input electrode of said first transmission gate is coupled to the output of said addition unit for receiving the reference voltage, and the input electrode of said first capacitor is coupled to the output electrode of said first transmission gate.

11. The circuit of claim 10, wherein said second sample and hold circuit comprises:

a second inverter having an input electrode and an output electrode;

a second capacitor having an input electrode and an output electrode; and

a second transmission gate having an input electrode, an output electrode, and first and second control electrodes, wherein the input electrode of said second inverter and the first control electrode of said second transmission gate are coupled for receiving the second clock signal, the output electrode of said second inverter is coupled to the second control electrode of said second transmission gate, the input electrode of said second transmission gate is coupled for receiving an output voltage from said first sample and hold unit, and the input electrode of said second capacitor is coupled to the output electrode of said second transmission gate.

12. The circuit of claim 7, wherein the first input electrode is coupled to an inverting input of said first operational amplifier, and said second input electrode is coupled to a non-inverting input of said first operational amplifier.

13. The circuit of claim 8, wherein the first input electrode is coupled to a non-inverting input of said second operational amplifier, and said second input electrode is coupled to an inverting input of said second operational amplifier.

14. The circuit of claim 5, wherein said sample and hold circuit comprises:

a first sample and hold circuit coupled to the output of said signal generating unit for receiving the reference voltage, and coupled for receiving a first clock signal; and

a second sample and hold unit coupled for receiving an output from said first sample and hold circuit, and coupled for receiving a second clock signal, wherein said first and second clock signals do not overlap.

15. The circuit of claim 14, wherein said first sample and hold circuit comprises:

a first inverter having an input electrode and an output electrode;

a first capacitor having an input electrode and an output electrode; and

a first transmission gate having an input electrode, an output electrode, and first and second control electrodes, wherein the input electrode of said first inverter and the first control electrode of said first transmission gate are coupled for receiving the first clock signal, the output electrode of said first inverter is coupled to the second control electrode of said first transmission gate, the input electrode of said first transmission gate is coupled to the output of said signal generating unit for receiving the reference voltage, and the input electrode of said first capacitor is coupled to the output electrode of said first transmission gate.

16. The circuit of claim 15, wherein said second sample and hold circuit comprises:

a second inverter having an input electrode and an output electrode;

a second capacitor having an input electrode and an output electrode; and

a second transmission gate having an input electrode, an output electrode, and first and second control electrodes, wherein the input electrode of said second inverter and the first control electrode of said second transmission gate are coupled for receiving the second clock signal, the output electrode of said second inverter is coupled to the second control electrode of said second transmission gate, the input electrode of said second transmission gate is coupled for receiving an output voltage from said first sample and hold unit, and the input electrode of said second capacitor is coupled to the output electrode of said second transmission gate.

17. The circuit of claim 16, wherein said signal generating unit comprises:

a non-linear unit with a sawtooth transfer characteristic for receiving the input voltage and generating the non-linear signal and

an addition unit for combining the non-linear signal with the externally applied voltage signal to provide the reference voltage.

18. The circuit of claim 14, wherein said signal generating unit comprises:

a non-linear unit with a sawtooth transfer characteristic for receiving the input voltage and generating the non-linear signal; and

an addition unit for combining the non-linear signal with the externally applied voltage signal to provide the reference voltage.