Method and apparatus for galvanically isolating two integrated circuits from each other

• US 6,124,756 A
• Filed: 04/08/1997
• Issued: 09/26/2000
• Est. Priority Date: 04/08/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yaklin, Daniel A., Kornher, Kevin Lee
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US08/835,888
• Time in Patent Office: 1,267 Days
• Field of Search: 327/379, 327/333, 327/538, 327/551, 327/564, 327/565, 327/309, 327/310, 327/318, 327/319, 326/30-34, 326/56, 326/62, 326/63, 326/80-83
• US Class Current: 327/564
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01759 with a bidirectional operation

Abstract

An isolation circuit (10) and method for providing dc isolation between two integrated circuit devices (11) and (12) that may be referenced to different ground potentials is presented. The isolation circuit (10) includes, in each circuit, an output buffer (20, 20'"'"') connected to deliver a signal to an input/output pin (16, 17) of the circuit (11, 12) with which the output buffer is associated. A capacitance (30), which may be a single capacitor or a combination of capacitors, is connected to the pins (16, 17) of each of the circuits (11, 12), and in each circuit (11, 12), an input buffer (22, 22'"'"') is connected to receive a signal delivered onto the I/O pin (16, 17). The input buffer (22, 22'"'"') includes a circuit for resisting a charge leakage from the capacitor, which, preferably is a bus holder circuit (36), or the like. In another embodiment, a transformer (85) is used to provide dc isolation between the two integrated circuits (62, 64).

Claims

1. An isolation circuit for providing dc isolation between two circuits that may be referenced to different ground potentials, comprising:

an output buffer in one of said circuits connected to deliver a data signal to an output node, said data signal having a first voltage level and a second voltage level representing a first logic level and a second logic level, respectively;

an input buffer in another of said circuits connected to receive said data signal on an input node; and

a capacitance connected between said output and input nodes;

said input buffer comprising a circuit for maintaining a last voltage level asserted at said input node and for resisting a charge leakage from said capacitance.

2. The circuit of claim 1 wherein said capacitance is a single capacitor.

3. The circuit of claim 1 wherein said capacitance is more than one capacitor.

4. The circuit of claim 1 wherein said data signal is a digital signal.

5. The circuit of claim 1 wherein said two circuits to be isolated are contained in respective first and second integrated circuit devices.

6. The circuit of claim 5 wherein said circuit for maintaining the last voltage level and resisting a charge leakage from said capacitance is a bus holder circuit.

7. The circuit of claim 6 wherein said bus holder circuit is internal to said second integrated circuit device.

8. The circuit of claim 6 wherein said bus holder circuit is external to said second integrated circuit device.

9. The circuit of claim 1 wherein said circuit for maintaining the last voltage level and resisting a charge leakage from said capacitor comprises a bus holder circuit.

10. The circuit of claim 9 wherein said bus holder provides less drive than said output buffer.

11. The circuit of claim 9 wherein said input buffer comprises a first inverter, and said bus holder comprises a second inverter connected in a reverse direction across said first inverter.

12. The circuit of claim 11 wherein said bus holder comprises a p-channel MOS device and an n-channel MOS device connected between a supply voltage and a ground potential, said MOS devices having gates connected to an output of said first inverter and drains connected to an input of said first inverter.

13. The circuit of claim 1 wherein said output node of said one of said circuits to be isolated is an input/output node, and further comprising a second input buffer contained in said one of said circuits to be isolated, said second input buffer having an input connected to said input/output node, and still further comprising a second circuit in said one of said circuits to be isolated for resisting a charge leakage from said capacitance.

14. A method for providing dc isolation between a first circuit from a second circuit, wherein a ground potential of said first circuit may be different from a ground potential of said second circuit, comprising:

connecting a capacitance between a signal output node of said first circuit and a signal input node of said second circuit;

providing a signal output buffer in said first circuit having an output connected to said output node for sourcing an signal output having a first voltage level and a second voltage level representing a first logic state and a second logic state, respectively;

providing a signal input buffer in said second circuit connected to said input node, said signal input buffer being constructed to hold a last asserted voltage level at said input of said input buffer despite charge leakage from said capacitance.

15. The method of claim 14 wherein said step of connecting a capacitance comprises connecting a plurality of interconnected capacitors to provide said capacitance.

16. The method of claim 14 wherein said step of connecting a capacitance comprises connecting a single capacitor to provide said capacitance.

17. The method of claim 14 wherein said step of providing a signal input buffer comprises providing a first inverter having an input connected to said input/output node and an output connected to said circuit, and providing a bus holder across said inverter to hold a current state of said inverter despite charge leakage from said capacitance.

18. The method of claim 17 wherein said step of providing a bus holder comprises providing a second inverter across said first inverter in an opposite direction from said first inverter.

19. The method of claim 18 wherein said step of providing a second inverter comprises providing a p-channel MOS device and an n-channel MOS device connected between a supply voltage and a ground potential, said MOS devices having gates connected to an output of said first inverter and drains connected to an input of said first inverter.

20. The method of claim 14 wherein said input node is an input/output node and further comprising providing a second signal output buffer in said second circuit, said second signal output buffer being connected to deliver an output signal to said input/output node.