Multiprocessor system with unit processors assigned a plurality of non-contiguous regions

• US 6,124,866 A
• Filed: 11/09/1993
• Issued: 09/26/2000
• Est. Priority Date: 05/10/1989
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Suzuki, Ryuta, Asano, Kenichi
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/150,548
• Time in Patent Office: 2,513 Days
• Field of Search: 395/163, 395/200, 395/650, 348/721, 345/505, 382/304, 709/105
• US Class Current: 345/505
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 19/98 Adaptive-dynamic-range coding [ADRC]

Abstract

An image processor has a plurality of unit processors, each of which are assigned specific non-contiguous frame regions. All of the unit processors simultaneously start processing input partial image signals after all of the signals corresponding to the assigned frame regions have been fetched.

Claims

1. An image processor having a plurality of unit processors which are programmed to be assigned frame regions of one picture frame, said unit processors each comprising:

a fetching unit for fetching input partial image signals corresponding to the frame regions assigned to the unit processor,

a processing unit for processing the input partial image signals after all of the input partial image signals corresponding to assigned frame regions have been fetched,

means for providing the processed signals to an output bus,

wherein each of said unit processors is assigned a plurality of frame regions which are not contiguous to each other, and

means for causing all the unit processors to simultaneously start processing the input partial image signals after all of the input partial image signals corresponding to the assigned frame regions have been fetched.

2. An image processor according to claim 1, wherein each of said unit processors has a storage unit for storing a signal processed therein, and the processed signal stored in said storage unit is read out to a common bus by a transfer control unit after completion of the signal processing operations in all said unit processors in such a manner that the readout signal can be fetched by another unit processor.

3. An image processor comprising:

a plurality of unit processors, at least some of which are programmed to be assigned to a plurality of non-contiguous frame regions for each frame, each of said unit processors comprising;

a fetching unit for fetching input partial image signals corresponding to the assigned non-contiguous frame regions;

a processing unit for processing the input partial image signals after all of the input partial image signals corresponding to assigned frame regions have been fetched, and

means for outputting the processed input partial image signals.

4. The image processor of claim 3 wherein each of the unit processors is assigned a plurality of non-contiguous frame regions.

5. The image processor of claim 4 further comprising means for starting processing of the input partial image signals simultaneously after all the signals corresponding to the assigned frame regions have been fetched.

6. The image processor of claim 5 further comprising a transfer control unit, wherein each of the unit processors further comprises a storage unit for storing signals processed by the unit processor, said stored signals being read out to a common bus by the transfer control unit after the signal processing in all said unit processors is completed, so that the signals read out can be fetched by the fetching unit of another unit processor.

7. A method for processing an image frame with a processor having a plurality of unit processors, the frame having frame regions, wherein each of the unit processors has a memory for storing a program which includes information concerning which frame regions are assigned to which unit processor, said method comprising the following steps:

assigning a plurality of non-contiguous frame regions to at least some of the unit processors by storing information concerning which frame regions are assigned to the unit processors in the memories of the unit processors;

fetching input signals corresponding to the plurality of frame regions;

processing each of the frame regions, after all of the input signals corresponding to the frame regions assigned to a unit processor have been fetched, resulting in processed signals; and

outputting the processed signals.

8. The method of claim 7 wherein each of the unit processors is assigned a plurality of non-contiguous frame regions.