Method for erasing nonvolatile memory cells in a field programmable gate array
First Claim
1. In an integrated circuit having a plurality of programmable interconnect cells, each cell selectively interconnecting first and second circuit nodes, each cell having a first transistor having a floating gate, a control gate, and first and second source/drain regions connected respectively to said first and second circuit nodes, and a second transistor having a floating gate connected to said floating gate of said first transistor, a control gate connected to said control gate of said first transistor, and first and second source/drain regions, a method of erasing said programmable interconnect cells comprisingasserting a first voltage of a first polarity on said control gates of said first and second transistors;
- asserting a ground voltage on said first and second source/drain regions of said first transistor; and
asserting a second voltage intermediate said first voltage and said ground voltage on said first and second source/drain regions of said second transistor.
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Abstract
In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.
24 Citations
5 Claims
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1. In an integrated circuit having a plurality of programmable interconnect cells, each cell selectively interconnecting first and second circuit nodes, each cell having a first transistor having a floating gate, a control gate, and first and second source/drain regions connected respectively to said first and second circuit nodes, and a second transistor having a floating gate connected to said floating gate of said first transistor, a control gate connected to said control gate of said first transistor, and first and second source/drain regions, a method of erasing said programmable interconnect cells comprising
asserting a first voltage of a first polarity on said control gates of said first and second transistors; -
asserting a ground voltage on said first and second source/drain regions of said first transistor; and asserting a second voltage intermediate said first voltage and said ground voltage on said first and second source/drain regions of said second transistor. - View Dependent Claims (2, 3, 4, 5)
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Specification
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- Resources
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Current AssigneeMicrosemi SoC Corp.
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Original AssigneeGateField Corp. (Microsemi SoC Corp.)
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InventorsHecht, Volker
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Primary Examiner(s)NGUYEN, TAN
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Application NumberUS09/311,975Time in Patent Office501 DaysField of Search365/185.18, 365/185.29, 326/39, 326/37, 326/38US Class Current365/185.29CPC Class CodesG11C 16/14 Circuits for erasing electr...
