Semiconductor memory device with high data read rate

• US 6,125,071 A
• Filed: 04/22/1999
• Issued: 09/26/2000
• Est. Priority Date: 04/22/1998
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toda, Haruki, Kohno, Fumihiro
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/296,268
• Time in Patent Office: 523 Days
• Field of Search: 365/230.03, 365/72
• US Class Current: 365/230.03
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.

Claims

1. A semiconductor memory device comprising:

a memory cell array having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs;

a row decoder for sequentially selecting said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected;

a plurality of sense amplifiers arranged in correspondence with each bit line pair, and configured to amplify data read out from a plurality of said memory cells to one of said bit line pairs; and

switch circuits provided between said sense amplifiers and said one bit line pair, and configured to connect said one bit line pair and said sense amplifiers.

2. A device according to claim 1, wherein each of said switch circuits comprises at least one transistor for connecting said one bit line pair and one of said sense amplifiers.

3. A device according to claim 1, wherein each of said switch circuits is turned on in synchronism with a selection operation of a word line to transfer data from said one bit line pair to a corresponding sense amplifier.

4. A device according to claim 1, wherein each of said sense amplifiers amplifies data in memory cells selected later in a first half of the multiple selection period of said plurality of word lines and restores the data in previously selected memory cells in a second half of the multiple selection period.

5. A device according to claim 1, wherein each of said sense amplifiers comprises a flip-flop formed by cross-connecting input and output terminals of a pair of CMOS inverters, and one of a PMOS transistor pair and an NMOS transistor pair which form said CMOS inverter is shared by said plurality of sense amplifiers.

6. A device according to claim 1, wherein said row decoder includes:

a decoding circuit having a synchronous logic circuit for decoding an external row address;

a plurality of latch circuits for sequentially latching an output signal from said decoding circuit with a phase difference; and

a driving circuit for driving a word line on the basis of signals latched by said latch circuits.

7. A semiconductor memory device comprising:

a plurality of memory cell arrays having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs;

a row decoder arranged in correspondence with each memory cell array to sequentially select said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected;

a plurality of first sense amplifiers arranged between adjacent memory cell arrays and shared by bit line pairs of said adjacent memory cell arrays, said first sense amplifiers configured to amplify data read out from said adjacent memory cells to said bit line pairs of said adjacent memory cells;

a global bit line pair formed commonly for said plurality of memory cell arrays;

a second sense amplifier connected to said global bit line pair, and configured to amplify data of said global bit line pair;

a plurality of first switch circuits formed between said first sense amplifiers and said bit line pairs of said memory cell arrays, said first switch circuits configured to connect said bit line pairs and said first sense amplifiers; and

a plurality of second switch circuits formed between said global bit line pair and said bit line pairs of said memory cell arrays, said second switch circuits configured to connect said global bit line pair and said bit line pairs.

8. A device according to claim 7, wherein each of said first switch circuits comprises at least one transistor for connecting one of said bit line pairs and one of said first sense amplifiers.

9. A device according to claim 7, wherein each of said first switch circuits is turned on in synchronism with a selection operation of a word line to transfer data from one of said bit line pairs to a corresponding first sense amplifier, and each of said second switch circuits is turned on in synchronism with the selection operation of said word line to transfer data from said one bit line pair to said global bit line pair.

10. A device according to claim 7, wherein

said first and second sense amplifiers amplify data in memory cells selected later in a first half of the multiple selection period of said plurality of word lines and restore the data in previously selected memory cells in a second half of the multiple selection period.

11. A device according to claim 7, wherein each of said first and second sense amplifiers comprises a flip-flop formed by cross-connecting input and output terminals of a pair of CMOS inverters, and one of a PMOS transistor pair and an NMOS transistor pair which form said CMOS inverter is shared by another one of said first and second sense amplifiers.

12. A device according to claim 7, wherein said row decoder includes:

a decoding circuit having a synchronous logic circuit for decoding an external row address;

a plurality of latch circuits for sequentially latching an output signal from said decoding circuit with a phase difference; and

a driving circuit for driving a word line on the basis of signals latched by said latch circuits.

13. A semiconductor memory device comprising:

first and second memory cell arrays having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs;

a row decoder arranged in correspondence with each of said first and second memory cell arrays to sequentially select said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected;

first and second sense amplifiers arranged in correspondence with each bit line pair of said first and second memory cell arrays, and configured to amplify data of one of said bit line pairs; and

first switch circuits formed between said first and second sense amplifiers and a bit line pair of said first memory cell array, said first switch circuits configured to selectively connect said first and second sense amplifiers and said bit line pair of said first memory cell array; and

second switch circuits formed between said first and second sense amplifiers and a bit line pair of said second memory cell array, said second switch circuits configured to selectively connect said first and second sense amplifiers and said bit line pair of said second memory cell array.

14. A device according to claim 13, wherein said first switch circuits comprise first and second transistors for connecting one of said bit line pairs of said first memory cell array and a first sense amplifier and third and fourth transistors for connecting said one bit line pair of said first memory cell array and a second sense amplifier.

15. A device according to claim 13, wherein said second switch circuits comprise first and second transistors for connecting one of said bit line pairs of said second memory cell array and a first sense amplifier and third and fourth transistors for connecting said one bit line pair of said second memory cell array and a second sense amplifier.

16. A device according to claim 13, wherein one of said first switch circuits is turned on in synchronism with a selection operation of a word line to transfer data from one of said bit line pairs to a first sense amplifier, and one of said second switch circuits is turned on in synchronism with the selection operation of said word line to transfer data from one of said bit line pairs to a second sense amplifier.

17. A device according to claim 13, wherein

said first and second sense amplifiers amplify data in memory cells selected later in a first half of the multiple selection period of said plurality of word lines and restore the data in previously selected memory cells in a second half of the multiple selection period.

18. A device according to claim 13, wherein each of said first and second sense amplifiers comprises a flip-flop formed by cross-connecting input and output terminals of a pair of CMOS inverters, and one of a PMOS transistor pair and an NMOS transistor pair which form said CMOS inverter is shared by another one of said first and second sense amplifiers.

19. A device according to claim 13, wherein said row decoder includes:

a decoding circuit having a synchronous logic circuit for decoding an external row address;

a plurality of latch circuits for sequentially latching an output signal from said decoding circuit with a phase difference; and

a driving circuit for driving a word line on the basis of signals latched by said latch circuits.

20. A semiconductor memory device, comprising:

a memory cell array having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs;

a row decoder for selecting said word lines;

a first sense amplifier arranged at one end portion of said bit line pair of said memory cell array to amplify data read out from memory cells to said bit line pair;

a second sense amplifier arranged at the other end portion of said bit line pair of said memory cell array to amplify data read out from memory cells to said bit line pair;

first switch circuits formed between said first sense amplifier and one end portion of said bit line pair to transfer data of said bit line pair to said first sense amplifier; and

second switch circuits formed between said second sense amplifier and the other end portion of said bit line pair to transfer data of said bit line pair to said second sense amplifier.

21. A device according to claim 20, wherein

said first and second switch circuits are turned on in synchronism with a selection operation of said word line to transfer data from said bit line pair to corresponding sense amplifiers.

22. A device according to claim 20, wherein

said first switch circuit is turned on in synchronism with a selection operation of said word line to transfer data from said bit line pair to a corresponding first sense amplifier, and said second switch circuit is turned on in synchronism with the selection operation of said word line to transfer data from said bit line pair to a corresponding second sense amplifier.

23. A device according to claim 20, wherein

said first and second sense amplifiers amplify data in memory cells selected later in a first half of the multiple selection period of said plurality of word lines and re-store the data in previously selected memory cells in a second half of the multiple selection period.

24. A device according to claim 20, wherein

each of said first and second sense amplifiers comprises a flip-flop formed by cross-connecting input and output terminals of a pair of CMOS inverters, and one of a PMOS transistor pair and an NMOS transistor pair which form said CMOS inverter is shared by said plurality of sense amplifiers.

25. A device according to claim 20, wherein said row decoder includes:

a decoding circuit having a synchronous logic circuit for decoding an external row address;

a plurality of latch circuits for sequentially latching an output signal from said decoding circuit with a phase difference; and

a driving circuit for driving said word line on the basis of signals latched by said latch circuits.