Semiconductor memory device with high data read rate
First Claim
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1. A semiconductor memory device comprising:
- a memory cell array having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs;
a row decoder for sequentially selecting said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected;
a plurality of sense amplifiers arranged in correspondence with each bit line pair, and configured to amplify data read out from a plurality of said memory cells to one of said bit line pairs; and
switch circuits provided between said sense amplifiers and said one bit line pair, and configured to connect said one bit line pair and said sense amplifiers.
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Abstract
A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.
399 Citations
25 Claims
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1. A semiconductor memory device comprising:
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a memory cell array having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs; a row decoder for sequentially selecting said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected; a plurality of sense amplifiers arranged in correspondence with each bit line pair, and configured to amplify data read out from a plurality of said memory cells to one of said bit line pairs; and switch circuits provided between said sense amplifiers and said one bit line pair, and configured to connect said one bit line pair and said sense amplifiers. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory device comprising:
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a plurality of memory cell arrays having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs; a row decoder arranged in correspondence with each memory cell array to sequentially select said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected; a plurality of first sense amplifiers arranged between adjacent memory cell arrays and shared by bit line pairs of said adjacent memory cell arrays, said first sense amplifiers configured to amplify data read out from said adjacent memory cells to said bit line pairs of said adjacent memory cells; a global bit line pair formed commonly for said plurality of memory cell arrays; a second sense amplifier connected to said global bit line pair, and configured to amplify data of said global bit line pair; a plurality of first switch circuits formed between said first sense amplifiers and said bit line pairs of said memory cell arrays, said first switch circuits configured to connect said bit line pairs and said first sense amplifiers; and a plurality of second switch circuits formed between said global bit line pair and said bit line pairs of said memory cell arrays, said second switch circuits configured to connect said global bit line pair and said bit line pairs. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor memory device comprising:
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first and second memory cell arrays having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs; a row decoder arranged in correspondence with each of said first and second memory cell arrays to sequentially select said word lines, said row decoder having a multiple selection period when a plurality of word lines are simultaneously selected; first and second sense amplifiers arranged in correspondence with each bit line pair of said first and second memory cell arrays, and configured to amplify data of one of said bit line pairs; and first switch circuits formed between said first and second sense amplifiers and a bit line pair of said first memory cell array, said first switch circuits configured to selectively connect said first and second sense amplifiers and said bit line pair of said first memory cell array; and second switch circuits formed between said first and second sense amplifiers and a bit line pair of said second memory cell array, said second switch circuits configured to selectively connect said first and second sense amplifiers and said bit line pair of said second memory cell array. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A semiconductor memory device, comprising:
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a memory cell array having memory cells, word lines, and bit line pairs, said memory cells being arranged at intersections between said word lines and said bit line pairs; a row decoder for selecting said word lines; a first sense amplifier arranged at one end portion of said bit line pair of said memory cell array to amplify data read out from memory cells to said bit line pair; a second sense amplifier arranged at the other end portion of said bit line pair of said memory cell array to amplify data read out from memory cells to said bit line pair; first switch circuits formed between said first sense amplifier and one end portion of said bit line pair to transfer data of said bit line pair to said first sense amplifier; and second switch circuits formed between said second sense amplifier and the other end portion of said bit line pair to transfer data of said bit line pair to said second sense amplifier. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification