Delay-locked loop circuitry for clock delay adjustment

• US 6,125,157 A
• Filed: 02/06/1997
• Issued: 09/26/2000
• Est. Priority Date: 02/06/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Lee, Thomas H., Stark, Donald C., Johnson, Mark G., Garlepp, Bruno W., Horowitz, Mark A., Lau, Benedict C., Donnelly, Kevin S., Yu, Leung, Chau, Pak Shing, Chan, Yiu-Fai, Tran, Chanh Vi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US08/795,657
• Time in Patent Office: 1,328 Days
• Field of Search: 327/141, 327/158, 327/156, 327/160, 327/175, 327/233, 327/244, 327/261, 327/276, 331/14, 331/17, 331/25, 331/117 FE, 375/371, 375/375, 375/376, 375/358, 375/373
• US Class Current: 375/371
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

Claims

1. A method for generating an output clock with a predetermined phase relationship with an input clock, the method comprising the steps of:

selecting a pair of adjacent phase vectors from a set of phase vectors, each vector separated in time from an adjacent vector by a unit delay;

generating the output clock using an interpolator that receives the selected pair of phase vectors;

delaying the output clock from the interpolator by a delay equal to a multiple of the unit delay to produce a feedback clock;

adjusting the selection of a pair of adjacent phase vectors received by the interpolator so that the phase of the input clock lies between the selected pair of phase vectors;

detecting the difference in phase between the input clock and the feedback clock;

interpolating between the selected pair of adjacent phase vectors using the interpolator so that the feedback clock is in phase with the input clock based on the detected phase difference between the input clock and the feedback clock; and

wherein the output clock from the interpolator has the predetermined phase relationship with the input clock when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.

2. The method of claim 1, wherein the step of detecting the difference in phase includes the step of filtering the detected phase difference between the input clock and the feedback clock.

3. The method of claim 1, further comprising the step of storing the current selection of phase vectors and the current adjustment of the interpolator, wherein the current selection of phase vectors and the current adjustment of the interpolator are preserved during a period of time when the input clock not is not present or the set of phase vectors is not present.

4. The method of claim 1, wherein the multiple of the unit delay includes zero.

5. The method of claim 1, further comprising the step of delaying the output clock from the interpolator by a delay equal to a multiple of the unit delay to produce the output clock, wherein the output clock has a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

6. The method of claim 5, wherein the output clock may lead or lag the input clock by a multiple of the unit delay.

7. The method of claim 1, wherein the output clock from the interpolator is buffered with a first clock buffer to produce the output clock;

and

wherein the feedback clock is buffered with a second clock buffer to produce the feedback clock, the first and second clock buffers having substantially the same delay and the output clock having a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

8. Circuitry for generating an output clock having a predetermined phase relationship with an input clock, the circuitry comprising:

selection circuitry having as inputs a set of phase vectors and a selection control signal, each vector separated in time from an adjacent vector by a unit delay, the selection circuitry for selecting a pair of adjacent phase vectors from the set;

a phase interpolator circuit receiving the selected pair of adjacent phase vectors and a phase adjust signal and generating the output clock, the phase interpolator for adjusting the phase of the output clock;

at least one feedback delay element coupled to the output clock to produce a feedback clock, the feedback delay element delaying the feedback clock from the output clock by an amount equal to a multiple of the unit delay; and

a phase adjusting circuit receiving the input clock and the feedback clock, wherein the phase adjusting circuit produces the selection control signal for adjusting the selection of a pair of adjacent phase vectors produced by the selection circuitry so that the phase of the input clock lies between the selected pair of adjacent phase vectors and wherein the phase adjusting circuit produces the phase adjust signal for adjusting the phase interpolator so that the feedback clock is in phase with the input clock, wherein the output clock has the predetermined phase relationship with the input clock when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.

9. The circuitry of claim 8, wherein the multiple of the unit delay includes zero.

10. The circuitry of claim 8, wherein the output clock from the phase interpolator is buffered with a first clock buffer to produce the output clock and wherein the feedback clock is buffered with a second clock buffer to produce the feedback clock, the first and second clock buffers having substantially the same delay and the output clock having a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

11. The circuitry of claim 8, wherein the phase adjusting circuit comprises:

a phase detector receiving the input clock and the feedback clock, the phase detector for determining whether the feedback clock is in phase with the input clock and for producing a phase detector output based on the difference in phase between the feedback clock and the input clock; and

a control circuit receiving the phase detector output signal, the control circuit producing the selection control signal for adjusting the selection of a pair of phase vectors generated by the selection circuitry and producing the phase adjust signal for adjusting the phase interpolator.

12. The circuitry of claim 11, wherein the control circuit includes a digital storage circuit having state information for representing the currents election of phase vectors and the adjustment of the phase interpolator.

13. The circuitry of claim 12, wherein the state information of the digital storage circuit is preserved when the input clock not is not present or the set of phase vectors is not present.

14. The circuitry of claim 11, wherein the control circuit includes:

a counter circuit receiving the phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital-to-analog converter receiving the digital count and generating the phase adjust signal, wherein the phase adjust signal is an analog signal proportional to the digital count.

15. The circuitry of claim 11, wherein the control circuit includes:

a filter receiving the phase detector output signal and generating a filtered phase detector output signal for reducing loop jitter;

a counter circuit receiving the filtered phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital-to-analog converter receiving the digital count and generating the phase adjust signal, wherein the phase adjust signal is an analog signal proportional to the digital count.

16. The circuitry of claim 15, wherein the filter is a digital filter.

17. The circuitry of claim 8, further comprising:

a first duty cycle correcting amplifier receiving the feedback clock;

a second duty cycle correcting amplifier receiving the output clock; and

a duty cycle correcting circuit receiving the feedback clock and adjusting the first and second duty cycle correcting amplifiers such that the feedback clock and output clock have substantially the same duty cycle, wherein the duty cycle is substantially close to 50%.

18. Circuitry for generating an output clock signal having a predetermined phase relationship with an input clock signal, the circuitry comprising:

selection circuitry having as inputs a set of phase vector signals and a selection control signal, each phase vector signal separated in time from an adjacent phase vector signal by a unit delay, the selection circuitry for selecting a pair of adjacent phase vector signals from the set;

a phase interpolator circuit receiving the selected pair of adjacent phase vector signals and a phase adjust signal and generating a phase interpolator output clock signal, the phase interpolator circuit adjusting the phase of the phase interpolator output clock;

at least one output delay element to receive the phase interpolator output clock signal and to produce the output clock signal, the output delay element delaying the phase interpolator output clock signal by an amount equal to a multiple of the unit delay; and

a phase adjusting circuit receiving the input clock signal and the phase interpolator output clock signal, wherein the phase adjusting circuit produces the selection control signal for adjusting the selection of a pair of adjacent phase vector signals produced by the selection circuitry so that the phase of the input clock signal lies between the selected pair of adjacent phase vector signals and wherein the phase adjusting circuit produces the phase adjust signal for adjusting the phase interpolator so that the phase interpolator output clock signal is in phase with the input clock signal, wherein the output clock signal has the predetermined phase relationship with the input clock signal when the phase interpolator output clock signal is in phase with the input clock signal, the predetermined phase relationship being a multiple of the unit delay.

19. The circuitry of claim 18 further comprising:

at least one feedback delay element coupled to the phase adjusting circuit for delaying the phase interpolator output clock signal by an amount equal to a multiple of the unit delay.

20. The circuitry of claim 19, wherein the output clock signal may lead or lag the input clock signal by a multiple of the unit delay.