Clock distribution network

• US 6,125,217 A
• Filed: 06/26/1998
• Issued: 09/26/2000
• Est. Priority Date: 06/26/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Young, Ian A., Paniccia, Mario J., Thomas, Thomas P., Rao, Valluri R. M.
• Primary Examiner(s): Healy, Brian
• Application Number:
  US09/105,502
• Time in Patent Office: 823 Days
• Field of Search: 385/14, 385/24, 385/129, 385/130, 385/131, 395/555, 395/556, 395/557, 395/558, 395/559
• US Class Current: 385/14
• CPC Class Codes: G02B 6/4249 comprising arrays of active devices and fibres
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical

Abstract

A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.

Claims

1. A clock distribution network, comprising:

a clock receiver node disposed in a first semiconductor die, the clock receiver node providing a first clock signal;

a clock generation circuit disposed in the first semiconductor die, the clock generation circuit coupled to the clock receiver node to generate a second clock signal in phase with the first clock signal to clock a second semiconductor die; and

a first skew removal circuit included in the clock generation circuit, the first skew removal circuit coupled to the clock receiver node and coupled to a clock input of the second semiconductor die, the first skew removal circuit to generate the second clock signal in response to the first clock signal and a signal of the clock input of the second semiconductor die.

2. The clock distribution network of claim 1 wherein the clock generation circuit further generates a third clock signal in phase with the first clock signal to clock an input/output circuit of the first semiconductor die.

3. The clock distribution network of claim 1 wherein the first skew removal circuit further generates a third clock signal in phase with the first clock signal to clock an input/output circuit of the first semiconductor die.

4. The clock distribution network of claim 1 wherein the clock generation circuit further comprises a second skew removal circuit coupled to receive the first clock signal from the clock receiver node and coupled to a clock input of an input/output circuit of the first semiconductor die, the second skew removal circuit to generate a third clock signal in phase with the first clock signal in response to the first clock signal and a signal of the clock input of the input/output circuit of the first semiconductor die to clock the input/output circuit of the first semiconductor die.

5. The clock distribution network of claim 1 wherein the first skew removal circuit comprises a phase lock loop circuit coupled to receive the first clock signal from the clock receiver node and coupled to the clock input of the second semiconductor die, the phase lock loop circuit to generate the second clock signal.

6. The clock distribution network of claim 1 wherein the first skew removal circuit comprises a delay lock loop circuit coupled to receive the first clock signal from the clock receiver node and coupled to the clock input of the second semiconductor die, the delay lock loop circuit to generate the second clock signal.

7. The clock distribution network of claim 1 further comprising a divide-by-N circuit coupled between the clock receiver node and the clock generation circuit.

8. The clock distribution network of claim 1 wherein the first semiconductor die includes at least a front side and a back side, the clock receiver node configured to receive the optical pulses through the back side of the first semiconductor die.

9. The clock distribution network of claim 1 wherein the first semiconductor die includes at least a front side and a back side, the clock receiver node configured to receive the optical pulses through the front side of the first semiconductor die.

10. The clock distribution network of claim 1 further comprising:

an optical source to generate master optical pulses, the optical source included in a heat sink thermally coupled to the first semiconductor die; and

a diffractive optics element optically coupled between the optical source and the clock receiver node to generate the optical pulses received by the clock receiver node.

11. A method for distributing a clock, comprising:

receiving clock pulses with a clock receiver node disposed in a first semiconductor die to generate a first clock signal;

generating a second clock signal in phase with the first clock signal with a clock generation circuit disposed in the first semiconductor die;

clocking a second semiconductor die with the second clock signal;

receiving a signal of a clock input of the second semiconductor die; and

removing skew between the signal of the clock input of the second semiconductor die and the first clock signal.

12. The method of claim 11 including the step of converting a current generated in the clock receiver node in response to the clock pulses into the first clock signal.

13. The method of claim 11 including the steps of:

generating a third clock signal in phase with the first clock signal with the clock generation circuit; and

clocking an input/output circuit of the first semiconductor die with the third clock signal.

14. The method of claim 11 including the step of dividing the first clock signal by N.

15. The method of claim 11 wherein the first semiconductor die includes at least a front side and a back side, wherein the step of receiving the clock pulses includes the step of receiving the clock pulses through the back side of the first semiconductor die.

16. The method of claim 11 wherein the first semiconductor die includes at least a front side and a back side, wherein the step of receiving the clock pulses includes the step of receiving the clock pulses through the front side of the first semiconductor die.

17. The method of claim 11 including the steps of:

generating master clock pulses with an optical source disposed in a heat sink thermally coupled to the first semiconductor die; and

splitting the master clock pulses to generate the clock pulses received by the clock receiver node.

18. A system, comprising:

a first semiconductor die including a clock receiver node disposed therein, the clock receiver node configured to receive clock pulses to generate a first clock signal, the first semiconductor die further including a clock generation circuit disposed therein coupled to the clock receiver node to generate a second clock signal in phase with the first clock signal;

a second semiconductor die having a clock input coupled to the clock generation circuit to receive the second clock signal, the second semiconductor die configured to be clocked by the second clock signal and;

a first skew removal circuit included in the clock generation circuit, the first skew removal circuit coupled to the clock input of the second semiconductor die and coupled to the clock receiver node, the first skew removal circuit to generate the second clock signal in response to the first clock signal and a signal of the clock input of the second semiconductor die.

19. The system of claim 18 wherein the clock generation circuit further generates a third clock signal in phase with the first clock signal, the first clock signal coupled to an input/output circuit of the first semiconductor die.

20. The system of claim 19 wherein the first skew removal circuit further generates the third clock signal in response to the first clock signal and the signal of the clock input of the second semiconductor die.

21. The system of claim 19 wherein the clock generation circuit comprises:

a first skew removal circuit coupled to the clock input of the second semiconductor die and coupled to the clock receiver node, the first skew removal circuit to generate the second clock signal in response to the first clock signal and a signal of the clock input of the second semiconductor die; and

a second skew removal circuit coupled to a clock input of the input/output circuit of the first integrated circuit die and coupled to the clock receiver node, the second skew removal circuit to generate the third clock signal in response to the first clock signal and a signal of the clock input of the input/output circuit of the first integrated circuit die.

22. The system of claim 20 wherein the first skew removal circuit comprises a phase lock loop circuit coupled to the clock input of the second semiconductor die and coupled to the clock receiver node, the phase lock loop circuit to generate the second and third clock signals.

23. The system of claim 20 wherein the first skew removal circuit comprises a delay lock loop circuit coupled to the clock input of the second semiconductor die and coupled to the clock receiver node, the delay lock loop circuit to generate the second and third clock signals.

24. The system of claim 18 wherein the second semiconductor die comprises a chip set.

25. The system of claim 18 wherein the second semiconductor die comprises a memory circuit.